1. Adapted from the lecture notes of John Kubiatowicz (UCB)
CPSC 321 Computer Architecture and Engineering Lecture 7 Designing a Multi-cycle Processor
Adapted from the lecture notes of John Kubiatowicz (UCB)

2. Recap: A Single Cycle Datapath
Instruction<31:0>
nPC_sel
Instruction
Fetch Unit Rd Rt
<21:25>
<16:20>
<11:15>
<0:15>
RegDst
Clk 1
Mux Rs Rt Rs Rt Rd
Imm16
RegWr
ALUctr 5 5 5
MemtoReg
busA
Equal
MemWr Rw Ra Rb
busW
The result of the last lecture is this single-cycle datapath.
+1 = 6 min. (X:46) 32
32 32-bit
Registers
ALU 32
busB 32
Clk 32
Mux
Mux 32
WrEn
Adr 1 1
Data In 32
imm16
Extender
Data
Memory 32 16
Clk
ALUSrc
ExtOp

3. Recap: The “Truth Table” for the Main Controlop 6
ALU
(Local)
func 3
ALUop
ALUctr
RegDst
ALUSrc :
R-type
ori lw sw
beq
jump
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
Branch
Jump
ExtOp
ALUop (Symbolic) 1 x
“R-type” Or
Add
Subtract
xxx op
ALUop <2>
ALUop <1>
ALUop <0>
Now that we have taken care of the Local Control (ALU Control), let’s refocus our attention to the Main Controller.
The job of the Main Control is to look at the Opcode field of the instruction and generate these control signals for the datapath (RegDst, ... ExtOp) as well as the 3-bit ALUop field for the ALU Control.
Here, I have shown you the symbolic value of the ALUop field as well as the actual bit assignment.
For example here (2nd column), the R-type ALUop is encode as 100 and the Add operation (3rd column) is encoded as 000..
This is call a quote “Truth Table” unquote because if you think about it, this is like having the truth table rotates 90 degrees.
Let me show you what I mean by that.
+3 = 65 min. (Y:45)

4. The Big Picture: Where are We Now?
The Five Classic Components of a Computer
Today’s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath
Processor
Input
Control
Memory
So where are in in the overall scheme of things.
Well, we just finished designing the processor’s datapath.
Now I am going to show you how to design the control for the datapath.
+1 = 7 min. (X:47)
Datapath
Output

5. Abstract View of our single cycle processor
Main
Control op
ALU
control
fun
ALUSrc
Equal
ExtOp
MemRd
MemWr
nPC_sel
RegDst
RegWr
MemWr
ALUctr
Reg.
Wrt
Register
Fetch
ALU
Ext
Mem
Access PC
Next PC
Instruction
Fetch
Result Store
Data
Mem
looks like a FSM with PC as state

6. What’s wrong with our CPI=1 processor?
Arithmetic & Logical PC
Inst Memory
Reg File
ALU
mux
mux
setup
Load PC
Inst Memory
Reg File
ALU
Data Mem
mux
mux
setup
Critical Path
Store PC
Inst Memory
Reg File
ALU
Data Mem
mux
Branch PC
Inst Memory
Reg File
cmp
mux
Long Cycle Time
All instructions take as much time as the slowest
Real memory is not as nice as our idealized memory
cannot always get the job done in one (short) cycle

7. Reducing Cycle Time
Cut combinational dependency graph and insert register / latch
Do same work in two fast cycles, rather than one slow one
May be able to short-circuit path and remove some components for some instructions!
storage element
storage element
Acyclic
Combinational
Logic
Acyclic
Combinational
Logic (A) 
storage element
Acyclic
Combinational
Logic (B)
storage element

8. Basic Limits on Cycle Time
Next address logic
PC <= branch ? PC + offset : PC + 4
Instruction Fetch
InstructionReg <= Mem[PC]
Register Access
A <= R[rs]
ALU operation
R <= A + B
Control
MemRd
MemWr
RegWr
MemWr
nPC_sel
RegDst
ALUSrc
ALUctr
ExtOp
Reg.
File
Operand
Fetch
Exec
Instruction
Fetch
Mem
Access PC
Next PC
Result Store
Data
Mem

9. Partitioning the CPI=1 Datapath
Add registers between smallest steps
Place enables on all registers
Equal
MemRd
MemWr
RegWr
MemWr
nPC_sel
RegDst
ExtOp
ALUSrc
ALUctr
Reg.
File
Operand
Fetch
Exec
Instruction
Fetch
Mem
Access PC
Next PC
Result Store
Data
Mem

10. Example Multicycle Datapath
Ext
ALU
Reg.
File
Mem
Access
Data
Result Store
RegDst
RegWr
MemWr
MemRd S M
MemToReg
Equal
ALUctr
ALUSrc
ExtOp
nPC_sel E
Reg
File A PC IR
Next PC B
Instruction
Fetch
Operand
Fetch
Critical Path ?

11. Recall: Step-by-step Processor Design
Step 1: ISA => Logical Register Transfers
Step 2: Components of the Datapath
Step 3: RTL + Components => Datapath
Step 4: Datapath + Logical RTs => Physical RTs
Step 5: Physical RTs => Control

12. Step 4: R-type (add, sub, . . .) Logical Register Transfer
Physical Register Transfers
inst Logical Register Transfers
ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4
inst Physical Register Transfers
IR <– MEM[pc]
ADDU A<– R[rs]; B <– R[rt]
S <– A + B
R[rd] <– S; PC <– PC + 4
Time E
Reg.
File
Reg
File A S
Exec PC IR
Next PC
Inst. Mem B
Mem
Access M
Data
Mem

13. Step 4: Logical immed Logical Register Transfer
Physical Register Transfers
inst Logical Register Transfers
ORI R[rt] <– R[rs] OR ZExt(Im16); PC <– PC + 4
inst Physical Register Transfers
IR <– MEM[pc]
ORI A<– R[rs]; B <– R[rt]
S <– A or ZExt(Im16)
R[rt] <– S; PC <– PC + 4
Time E
Reg.
File
Reg
File A S
Exec PC IR
Next PC
Inst. Mem B
Mem
Access M
Data
Mem

14. Step 4 : Load Logical Register Transfer Physical Register Transfers
inst Logical Register Transfers
LW R[rt] <– MEM[R[rs] + SExt(Im16)];
PC <– PC + 4
Logical Register Transfer
Physical Register Transfers
inst Physical Register Transfers
IR <– MEM[pc]
LW A<– R[rs]; B <– R[rt]
S <– A + SExt(Im16)
M <– MEM[S]
R[rd] <– M; PC <– PC + 4
Time E
Reg.
File
Reg
File A S
Exec PC IR
Next PC
Inst. Mem B
Mem
Access M
Data
Mem

15. Step 4 : Store Logical Register Transfer Physical Register Transfers
inst Logical Register Transfers
SW MEM[R[rs] + SExt(Im16)] <– R[rt];
PC <– PC + 4
Logical Register Transfer
Physical Register Transfers
inst Physical Register Transfers
IR <– MEM[pc]
SW A<– R[rs]; B <– R[rt]
S <– A + SExt(Im16);
MEM[S] <– B PC <– PC + 4
Time E
Reg.
File
Reg
File A S
Exec PC IR
Next PC
Inst. Mem B
Mem
Access M
Data
Mem

16. Step 4 : Branch Logical Register Transfer Physical Register Transfers
inst Logical Register Transfers
BEQ if R[rs] == R[rt]
then PC <= PC + 4+SExt(Im16) || 00
else PC <= PC + 4
inst Physical Register Transfers
IR <– MEM[pc]
BEQ E<– (R[rs] = R[rt])
if !E then PC <– PC else PC <–PC+4+SExt(Im16)||00
Time E
Reg.
File
Reg
File S A
Exec PC IR
Next PC
Inst. Mem B
Mem
Access M
Data
Mem

17. Alternative data-path (book): Multiple Cycle Datapath
Minimizes Hardware: 1 memory, 1 adder
PCWr
PCWrCond
PCSrc
BrWr
Zero
IorD
MemWr
IRWr
RegDst
RegWr
ALUSelA 1
Target 32 32
Mux PC
Mux 1 32
Zero Rs
Mux 1 Ra 32
RAdr 5 32 Rt Rb
busA 32 32
ALU
Putting it all together, here it is: the multiple cycle datapath we set out to built.
+1 = 47 min. (Y:47)
Ideal
Memory
Instruction Reg 5
Reg File 32
ALU Out
Mux 1 Rt 4 Rw 32
WrAdr 32 32 Rd 1 32
Din
Dout
busW
busB 32 32 2
ALU
Control
Mux 1 3
<< 2
Extend 16
Imm 32
ALUOp
ExtOp
MemtoReg
ALUSelB

18. Our Control Model State specifies control points for Register Transfer
Transfer occurs upon exiting state (same falling edge)
inputs (conditions)
Next State
Logic
State X
Register Transfer
Control Points
Control State
Depends on Input
Output Logic
outputs (control points)

19. Step 4  Control Specification for multicycle proc
“instruction fetch”
IR <= MEM[PC]
A <= R[rs]
B <= R[rt]
“decode / operand fetch” LW
R-type
ORi SW
BEQ
Execute
Memory
Write-back
S <= A fun B
S <= A or ZX
S <= A + SX
S <= A + SX
PC <=
Next(PC,Equal)
M <= MEM[S]
MEM[S] <= B
PC <= PC + 4
R[rd] <= S
PC <= PC + 4
R[rt] <= S
PC <= PC + 4
R[rt] <= M
PC <= PC + 4

20. Traditional FSM Controller
next
state
state op
cond
control points
Truth Table
next
State
control points 11
Equal 6
State 4 op
datapath State

21. Step 5  (datapath + state diagram control)
Translate RTs into control points
Assign states
Then go build the controller

22. Mapping RTs to Control Points
IR <= MEM[PC]
“instruction fetch”
imem_rd, IRen
A <= R[rs]
B <= R[rt]
“decode”
Aen, Ben,
Een LW
R-type
ORi SW
BEQ
Execute
Memory
Write-back
S <= A fun B
S <= A or ZX
S <= A + SX
S <= A + SX
PC <=
Next(PC,Equal)
ALUfun, Sen
M <= MEM[S]
MEM[S] <= B
PC <= PC + 4
R[rd] <= S
PC <= PC + 4
RegDst,
RegWr,
PCen
R[rt] <= S
PC <= PC + 4
R[rt] <= M
PC <= PC + 4

23. Assigning States “instruction fetch” IR <= MEM[PC] 0000 “decode”
A <= R[rs]
B <= R[rt]
“decode”
0001 LW
R-type
ORi SW
BEQ
Execute
Memory
Write-back
S <= A fun B
S <= A or ZX
S <= A + SX
S <= A + SX
PC <= Next(PC)
0100
0110
1000
1011
0011
M <= MEM[S]
MEM[S] <= B
PC <= PC + 4
1001
1100
R[rd] <= S
PC <= PC + 4
R[rt] <= S
PC <= PC + 4
R[rt] <= M
PC <= PC + 4
0101
0111
1010

24. (Mostly) Detailed Control Specification (missing0)
State Op field Eq Next IR PC Ops Exec Mem Write-Back
en sel A B E Ex Sr ALU S R W M M-R Wr Dst
0000 ?????? ?
0001 BEQ x
0001 R-type x
0001 ORI x
0001 LW x
0001 SW x
0011 xxxxxx x x
0011 xxxxxx x x
0100 xxxxxx x fun 1
0101 xxxxxx x
0110 xxxxxx x or 1
0111 xxxxxx x
1000 xxxxxx x add 1
1001 xxxxxx x
1010 xxxxxx x
1011 xxxxxx x add 1
1100 xxxxxx x
-all same in Moore machine
BEQ: R:
ORi:
LW:
SW:

25. Performance Evaluation
What is the average CPI?
state diagram gives CPI for each instruction type
workload gives frequency of each type
Type CPIi for type Frequency CPIi x freqIi
Arith/Logic 4 40% 1.6
Load 5 30% 1.5
Store 4 10% 0.4
branch 3 20% 0.6
Average CPI: 4.1

26. Use this structure to construct a simple “microsequencer”
Controller Design
The state digrams that arise define the controller for an instruction set processor are highly structured
Use this structure to construct a simple “microsequencer”
Control reduces to programming this very simple device
 microprogramming
sequencer
control
datapath control
micro-PC
microinstruction

27. Our Microsequencer taken datapath control Z I L Micro-PC op-code
Map ROM

28. Microprogram Control Specification
µPC Taken Next IR PC Ops Exec Mem Write-Back
en sel A B Ex Sr ALU S R W M M-R Wr Dst
0000 ? inc 1
load 1 1
zero
zero
0100 x inc fun 1
0101 x zero
0110 x inc or 1
0111 x zero
1000 x inc add 1
1001 x inc
x zero
1011 x inc add 1
1100 x zero
BEQ R:
ORi:
LW:
SW:

29. “microprogrammed control”
Overview of Control
Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.
Initial Representation Finite State Diagram Microprogram
Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs
Logic Representation Logic Equations Truth Tables
Implementation PLA ROM Technique
“hardwired control”
“microprogrammed control”

30. Microprogramming (Maurice Wilkes)
Control is the hard part of processor design
° Datapath is fairly regular and well-organized
° Memory is highly regular
° Control is irregular and global
Microprogramming:
-- A Particular Strategy for Implementing the Control Unit of a
processor by "programming" at the level of register transfer
operations
Microarchitecture:
-- Logical structure and functional capabilities of the hardware as
seen by the microprogrammer
Historical Note:
IBM 360 Series first to distinguish between architecture & organization
Same instruction set across wide range of implementations, each with
different cost/performance

31. “Macroinstruction” Interpretation
User program
plus Data
this can change!
Main
Memory
ADD
SUB
AND .
one of these is
mapped into one
of these
DATA
execution
unit
CPU
control
memory
AND microsequence
e.g., Fetch
Calc Operand Addr
Fetch Operand(s)
Calculate
Save Answer(s)

32. To DataPath Microprogramming -Code ROM
datapath control
microinstruction ()
sequencer
control
micro-PC
-sequencer:
fetch,dispatch,
sequential
Dispatch
ROM
Opcode
Inputs
-Code ROM
To DataPath
Decode
Microprogramming is a fundamental concept
implement an instruction set by building a very simple processor and interpreting the instructions
essential for very complex instructions and when few register transfers are possible
overkill when ISA matches datapath 1-1

33. Designing a Microinstruction Set
1) Start with list of control signals
2) Group signals together that make sense (vs. random): called “fields”
3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)
4) To minimize the width, encode operations that will never be used at the same time
5) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals
Use computers to design computers

34. 1&2) Start with list of control signals, grouped into fields
Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd MemRead None Memory at address is read, MDR <= Mem[addr] MemWrite None Memory at address is written IorD Memory address = PC Memory address = S IRWrite None IR <= Memory PCWrite None PC <= PCSource PCWriteCond None IF ALUzero then PC <= PCSource PCSource PCSource = ALU PCSource = ALUout ExtOp Zero Extended Sign Extended
Single Bit Control
Signal name Value Effect ALUOp 00 ALU adds ALU subtracts ALU does function code 11 ALU does logical OR ALUSelB 00 2nd ALU input = nd ALU input = Reg[rt] nd ALU input = extended,shift left nd ALU input = extended
Multiple Bit Control

35. 3&4) Microinstruction Format: unencoded vs. encoded fields
Field Name Width Control Signals Set
wide narrow
ALU Control 4 2 ALUOp
SRC1 2 1 ALUSelA
SRC2 5 3 ALUSelB, ExtOp
ALU Destination 3 2 RegWrite, MemtoReg, RegDst
Memory 3 2 MemRead, MemWrite, IorD
Memory Register 1 1 IRWrite
PCWrite Control 3 2 PCWrite, PCWriteCond, PCSource
Sequencing 3 2 AddrCtl
Total width bits

36. 5) Legend of Fields and Symbolic Names
Field Name Values for Field Function of Field with Specific Value ALU Add ALU adds Subt. ALU subtracts Func code ALU does function code Or ALU does logical OR SRC1 PC 1st ALU input = PC rs 1st ALU input = Reg[rs] SRC2 4 2nd ALU input = 4 Extend 2nd ALU input = sign ext. IR[15-0] Extend0 2nd ALU input = zero ext. IR[15-0] Extshft 2nd ALU input = sign ex., sl IR[15-0] rt 2nd ALU input = Reg[rt] destination rd ALU Reg[rd] = ALUout rt ALU Reg[rt] = ALUout rt Mem Reg[rt] = Mem Memory Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr Memory register IR IR = Mem PC write ALU PC = ALU ALUoutCond IF ALU Zero then PC = ALUout Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch Dispatch using ROM.
Note: can specify combinations of fields that may not be possible or not work properly given the datapath (e.g., ALU operand and write register in single cycle)

37. Quick check: what do these fieldnames mean?
Destination:
Code Name RegWrite MemToReg RegDest
X X
01 rd ALU 1 0 1
10 rt ALU 1 0 0
11 rt MEM 1 1 0
SRC2:
Code Name ALUSelB ExtOp
X X X
010 rt 01 X
011 ExtShft 10 1
100 Extend 11 1
111 Extend0 11 0

38. Specific Sequencer 1 microPC Adder Mux 2 µAddress ROM Select Logic
Sequencer-based control unit
Called “microPC” or “µPC” vs. state register
Code Name Effect fetch Next µaddress = dispatch Next µaddress = dispatch ROM seq Next µaddress = µaddress + 1
ROM:
Opcode
microPC 1
µAddress
Select
Logic
Adder
ROM
Mux 2
R-type
BEQ
ori LW SW

39. Microprogram it yourself!
Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write Sequencing
Fetch: Add PC 4 Read PC IR ALU Seq

40. Microprogram it yourself!
Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write Sequencing
Fetch: Add PC 4 Read PC IR ALU Seq
Add PC Extshft Dispatch
Rtype: Func rs rt Seq
rd ALU Fetch
Lw: Add rs Extend Seq
Read ALU Seq
rt MEM Fetch
Sw: Add rs Extend Seq
Write ALU Fetch
Ori: Or rs Extend Seq
rt ALU Fetch
Beq: Subt. rs rt ALUoutCond. Fetch

41. Microprogramming Pros and Cons
Ease of design
Flexibility
Easy to adapt to changes in organization, timing, technology
Can make changes late in design cycle, or even in the field
Can implement very powerful instruction sets (just more control memory)
Generality
Can implement multiple instruction sets on same machine.
Can tailor instruction set to application.
Compatibility
Many organizations, same instruction set
Costly to implement
Slow

42. Summary Microprogramming is a fundamental concept
implement an instruction set by building a very simple processor and interpreting the instructions
essential for very complex instructions and when few register transfers are possible
Control design reduces to Microprogramming
Design of a Microprogramming language
Start with list of control signals
Group signals together that make sense (vs. random): called “fields”
Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)
To minimize the width, encode operations that will never be used at the same time
Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals