SYNTHESIS OF COPPER NANOWIRES WITH NANO- TWIN SUBSTRUCTURES 1 Joon-Bok Lee 2 Dr. Bongyoung I. Yoo 2 Dr. Nosang V. Myung 1 Department of Chemical Engineering,
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Presentation on theme: "SYNTHESIS OF COPPER NANOWIRES WITH NANO- TWIN SUBSTRUCTURES 1 Joon-Bok Lee 2 Dr. Bongyoung I. Yoo 2 Dr. Nosang V. Myung 1 Department of Chemical Engineering,"— Presentation transcript:
SYNTHESIS OF COPPER NANOWIRES WITH NANO- TWIN SUBSTRUCTURES 1 Joon-Bok Lee 2 Dr. Bongyoung I. Yoo 2 Dr. Nosang V. Myung 1 Department of Chemical Engineering, A-217 Engineering Quadrangle, Princeton University, Princeton, NJ 08544-5263, USA 2 Department of Chemical Engineering, University of California, Riverside, CA 92521, USA
Outline Purpose of Research –Usage of copper nanowires in VLSI (very- large scale integration) Objective of Research Experimental Procedures –Copper thin film electrodeposition –Template-based copper nanowire fabrication Results and Discussions
Introduction Integrated circuit –Discovery in 1970-driving force in advent of computer systems –Contain transistors and other semiconducting devices –metal interconnections that serve as interconnections for each component –1997: Electrodeposited Copper replaces sputtered Aluminum as interconnecting material Much higher conductivity and lower electromigration
Introduction Advancements in technology increasing interconnections in smaller areas –International Technology Roadmap for Semiconductors (ITRS) 2005: 100 million transistors, 100,000 I/O in 30nm 2 chips by 2015 Copper wires must also be reduced to the nanometer scale –Need high electrical conductivity and tensile strength
A cross section of a microchip showing copper interconnections.
Introduction strength of materials increase with decreasing grain sizes that form the materials –Smaller grain sizes give greater grain boundaries (GB) –GBs resist propagation of dislocations –But GBs also scatter electrons-higher resistance Twin Boundary (TB) blocks dislocation but maintains conductivity Optimum: find methods to make nanowires with TBs –No known attempts in literature or otherwise
An example of twin boundaries found within specially prepared copper thin film samples Grain Boundary
Objective Understand effect of electrodeposition conditions for synthesizing copper nano- twinned nanowires Investigate meterials properties, including morphology and microstructures, of copper nanowires Investigate electrical properties of copper nanowires by measuring temperature dependent electrical resistivity
Determination of electrodeposition conditions –Form contiguous copper thin films without powdery deposits Plated on Brass substrates with 99.9% copper as anode Acid copper electrolyte Direct Current and Pulse-reverse current tested Selective chemical etching for grain size observation Procedure
Electrodeposition of Copper nanowires Procedure Anodization of Al to form alumina templates –A) clean and cut Al to appropriate size –B) Anodization of Al 20V Al anode Platinum coated Titanium cathode –C) formation of hexagonally close packed Alumina Average pore size 30nm –D), E) selective chemical etching D) Aluminum backing E) Barrier layer etching to open pores
Electrodeposition of Copper nanowires Procedure –F) Sputter Au seed layer To form working conductive electrode –G) Place templates on glass slide to form workable electrode Copper tape and silver paint used to form electrical connection –H), I) electrodeposition of nanowires Same electrolyte solution –J), K) Isolation of alumina template with enclosed nanowires J) removal from glass slide through acetone E) mechanical removal of gold seed layer –L) Chemical dissolution of alumina template
Grain Size versus Current Density Grain size decreases as direct current is increased. Agitation increases grain size. Increasing current
Prelim. Grain Size Tests Figure 3. Grain size was similar or slightly decreased in reverse-forward plating as compared to direct current plating
Prelim. Grain Size Tests Figure 4. The efficacy was nearly 100% for most of current density conditions.
Prelim. Dep. Rate Tests Figure 5. The deposition rate seems to linearly increase as a function of current density.
Alumina Templates Figure 8. alumina template cross sections, taken after 2hours, 3hours, and 4 hours of oxidation. (19, 44, 65 micrometers, respectively) 2 hours3 hours4 hours
Alumina Templates Figure 9. The thickness seems to linearly increase as a function of time in oxidation.
Templates with enclosed nanowires Nanowire deposition in custom alumina templates. Processed nanowires from the same template.
Future Plans Further nanowires have been made with custom anodized alumina templates Further nanowires have been made with custom anodized alumina templates –sent to TEM for imaging and confirmation of nanotwin structure growth If nanotwin structures within the nanowires are confirmed –further testing to find out the optimum current condition and other aspects will be done
Acknowledgement I would like to thank: Dr. B.Y. Yoo Dr. Nosang Myung UCR NSF REU BRITE program UCR Nano Electrochemical System Laboratory (NESL)