1. Exception Processing ECE511: Digital System & Microprocessor

2. What we are going to learn in this session: What are exceptions. How M68k handles exceptions. M68k execution states and how they relate to exception handling.

3. Introduction

4. Exceptions Out-of-ordinary events that happen during M68k run-time. Caused by:  Interrupt requests.  Errors during processing cycle.  Arithmetic operations that cannot be completed.  Illegal instructions.

5. Exception Example (Divide by Zero) MOVE.W#0,D0 MOVE.L#500000, D1 DIVUD0,D1 500,000 / 0 = ? * Divide by Zero Exception

6. Exception Example: Address Error Memory range = $000000 to $004000 MOVE.B#$0A,$004500 $0000 $0001 $0002 … … $3FFE $3FFF $4000 $4500? (Address out of range) * Address Error Exception

7. Exception Example: Address Error MOVE.B#$A00A,$000001 $0000 $0001 $0002 … … $3FFE $3FFF $4000 Word transfer to odd address. * Address Error Exception

8. External peripheral asks for attention by outputting interrupt on IPL 0, IPL 1, IPL 2. Exception Example: Interrupt Request M68k External Peripheral 1 M68k is executing instructions normally. 2 External peripheral has important task for M68k. 3 M68k compares interrupt level to SR. 4 TSI2I2 I1I1 I0I0 XNZVC M68k services/holds interrupt based on interrupt level 5

9. Exception Example: Spurious Interrupt S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 CLK A 1 – A 23 AS LDS/UDS R/W DTACK D 0 – D 15 FC 0 – FC 2 DTACK never responds

10. Exceptions Exceptions should be handled properly:  Can cause data loss.  System failure.  No prioritizing of tasks. M68k handles exceptions using Exception Handling.

11. M68k Execution States

12. M68k always functions in either of the three states:  Normal.  Halted.  Exception.

13. Normal State M68k operating normally. Executing in user mode (S=0). Has a restricted instruction set:  Can’t execute privileged instructions.  Prevents from executing potentially destructive instructions. Reserved for SV.

14. Restricted Commands in Normal State STOP RESET RTE Any commands that modify the SR. MOVE USP

15. Exception State Handles special events (exceptions), then returns to normal execution. Can execute all instructions. Always saves processor context before handling exception, restored when returned to normal execution. Always executes in SV mode (S=1).

16. The Status Register TSI2I2 I1I1 I0I0 XNZVC Supervisor Mode, S = 1 (Exception State, Halted State) User Mode, S = 0 (Normal State)

17. Halted State M68k stops execution of all instructions. Done by activating HALT line:  Stops execution after current instruction.  Waits until HALT is inactive.  Resumes normal execution.

18. Halted State Reason:  Catastrophic system failures (double bus faults, hardware failure).  User: intentionally activating the HALT line. Purpose:  Protect data inside memory.

19. How States are Changed NormalHaltedException Double bus fault/User-initiated S=0, RTE, Edit SR S=1, Exceptions, Interrupt Reset Exception User-initiated

20. Exception Handling

21. Series of steps performed to handle exceptions. Ensures exceptions processed properly & resume normal execution. Allows M68k to:  Save all processor status before exception.  Handle the exception.  Restore processor status when exception has been handled.

22. What Happens During an Exception? Contents of SR saved to memory. S bit is set. Exception vector is obtained. Processor context (PC & SR) saved on software stack. PC set to address of exception vector. Execution resumes from new PC location. Control and context restored & execution resumes from last address before exception.

23. Exception Handler Operation TRAPV Save PC and SR to stack. Read handler address from Vector Table. Read original PC and SR from stack. Save D0-D7, A0-A7 Handler Code Reload D0-D7, A0-A7 RTE Next Instruction

24. Exception Processing Steps

25. 1. Adjust SR. 2. Get Vector Number. 3. Save processor information. 4. Fetch new PC. 5. Restore context, resume last instruction in Normal mode.

26. Step 1: Adjust SR To enter SV state and prepare for exception processing:  Store SR internally.  Set S = 1 (SV Mode).  Set T = 0 (Disable Tracing).  If interrupt, update Interrupt Mask Bits.

27. SR Bits Modified by Step 1 TSI2I2 I1I1 I0I0 XNZVC S = 1T = 0 Updated if: I REQ > I CURRENT

28. Step 2: Get Vector Number Determines what type of exception, and get location of its appropriate handler. VN: 8-bit value indicating exception type.  Supplied by external device or M68k.  What kind of exception is happening.  Ranges from $00 (0) to $FF (255). VN used to find Vector Address (VA).

29. Vector Address (VA) Special memory location that stores addresses of exception handlers. VA obtained by multiplying VN with 4.  VN x 4 = VA. VA contains a long-word value containing address of exception handler. Contents inside VA loaded into PC, execution continued at this location.

30. How Exception Handling Works 1.VN given by external circuit/M68k. Based on VN, M68k knows what type of exception has occurred. VA = VN x 4 VN 2. VN x 4 = VA. Address of exception handler contained inside VA. M68k loads value into PC. $0000xxx $0004xxx $0008$3000 $000Cxxx $0010xxx PC$3000 3. M68k saves registers into stack, execution resumes at exception handler address. $3000 $3002 $3004 $0006 $0018 Exception handler code RTE

31. Vector Table (Antonakos, pg. 110) VNAssignment 0Reset: Initial SSP and PC 2Bus Error 3Address Error 5Divide by Zero 8Privilege Violation 9Trace 24Spurious Interrupt 25-31Interrupt Auto-vectors 32-47TRAP Instruction Vectors VA = VN x 4 0 = $0000 $0064 - $007C $0080 – 00BC 96 = $0060 36 = $0024 32 = $0020 20 = $0014 12 = $000C 8 = $0008

32. Step 3: Save Processor Information Saves processor context into stack:  PC: next instruction after exception processing.  SR.  Bus cycle attempted, part of instruction (for bus error and address error). SSP is used  already in SV mode.

33. How Context Saved into Stack – Typical Exception Status Register PC (High Word) PC (Low Word) Old SSP location  New SSP location 

34. How Context Saved into Stack PC = $001111 SR = $0115 SSP = $002FFF $0115 $0000 $1111 … $002FFF $002FFD $002FFB $002FF8 SSP SSP-2 SSP-4 SSP-6 Old SSP location  New SSP location 

35. Step 4: Fetch New PC Loads PC from vector table in Step 2. Processing resumes at exception handler. Returned to normal processing using (Return to Exception) RTE.

36. Exception Handler Contains instructions on how to process the exception. Located in SV memory space. RTE at the end, resumes normal execution.

37. Exception Handler Contents Save Registers Handler Code Reload Registers RTE (Return to Exception) Save Registers, PC into Stack Code to handle exception Reload Registers from Stack Reload PC from stack, execution resumes at next instruction after exception.

38. Exception Example (Divide by Zero) MOVE.W#0,D0 MOVE.L#500000, D1 DIVUD0,D1 PC = $1040 SR = 500,000 / 0 = ? * Divide by Zero Exception TSIIIXNZVC 0000000000101100 0016

39. Step 1: Adjust SR Store SR internally. Set S = 1 (SV Mode). Set T = 0 (Disable Tracing). If interrupt, update Interrupt Mask Bits.

40. Step 1: Adjust SR TSIIIXNZVC 0010000000101100 T = 0S = 1 Not interrupt = unchanged

41. Step 2: Get Vector Number Divide by zero exception VN is VN = 5 VN x 4 used to find Vector Address (VA). VA = VN x 4 = 20 = $000014

42. Vector Address (VA) Special memory location that stores addresses of exception handlers. VA obtained by multiplying VN with 4.  VN x 4 = VA. VA contains a long-word value containing address of exception handler. Contents inside VA loaded into PC, execution continued at this location.

43. Vector Table Value $00400500 $00400600 $00400700 $00400800 $00400900 $00400A00 $00400B00 Address $0000 $0060 $0024 $0020 $0014 $000C $0008

44. Step 3: Save Processor Information Saves processor context into stack. SSP is used  already in SV mode. PC =$001040 SSP/A7 = $004000 SR = $0016 $0016 (SR) $0000 (PC) $1040 (PC) Old SSP  $4000 New SSP  $3FFA

45. Step 4: Fetch New PC Loads PC from vector table in Step 2. Processing resumes at exception handler. Value $00400500 $00400600 $00400700 $00400800 $00400900 $00400A00 $00400B00 Address $0000 $0060 $0024 $0020 $0014 $000C $0008 New PC = $00400800 

46. Exception Handler Contents Save D0-D7, A0–A7 Handler Code Reload D0-D7, A0-A7 RTE (Return to Exception) Save Registers into Stack Code to handle exception Reload Registers from Stack Reload PC, SR from stack, execution resumes at next instruction after DIVU. $00400800

47. Handling Multiple Exceptions

48. It is possible for another exception to happen when the current exception is being handled.  An bus error occurs when M68k is handling an interrupt.  A trace exception generated during a divide by zero exception.

49. How does M68k handle multiple exceptions? In M68k, each exception has priority level:  Reset exception has higher priority than Trace exception.  An interrupt exception is more important than a Divide-by-Zero exception. When multiple exceptions happen, the more important one executed first.

50. Exception Grouping & Priority GroupExceptionPriority Reset Bus Error Address Error Trace Interrupt Illegal Privilege TRAP TRAPV CHK Zero Divide 0 (Highest) (Lowest) 1 (Highest) (Lowest) 2 All have same priority. Importance

51. Handling Multiple Exceptions Exceptions divided into 3 priority levels:  The higher-up, the more important.  Group 0 > Group 1 > Group 2.  Reset > Bus Error > Address Error > …..

52. What happens during multiple exceptions? The new exception compared to the current exception being handled:  If higher, creates an exception inside an exception: Saves processor context into stack. Handle new exception. Restore context from stack, return to old exception handle.  If lower, wait, then handle new exception. Save new exception request. Wait until current exception finishes. Handle new exception.

53. New < Old Exception - Example During a Trace exception (T = 1), an interrupt request has occurred. How would M68k handle this situation?

54. Exception Grouping & Priority GroupExceptionPriority Reset Bus Error Address Error Trace Interrupt Illegal Privilege TRAP TRAPV CHK Zero Divide 0 (Highest) (Lowest) 1 (Highest) (Lowest) 2 All have same priority. Trace exception higher than interrupt. Trace will be handled first.

55. New < Old Exception EXG (D0,D1) Trace Handler Save context Interrupt Handler Restore Context *Trace Handler executed first, then Interrupt Handler executed.

56. New > Old Exception - Example During an Interrupt exception, an Address Error Exception has occurred. How would M68k handle this situation?

57. Exception Grouping & Priority GroupExceptionPriority Reset Bus Error Address Error Trace Interrupt Illegal Privilege TRAP TRAPV CHK Zero Divide 0 (Highest) (Lowest) 1 (Highest) (Lowest) 2 All have same priority. Address Error exception higher than Interrupt. Address Error will be handled first.

58. New > Old Exception EXG (D0,D1) Interrupt Handler Save context Address Error Handler Restore Context Ins. in Handler *Address Error Handler executed first, then Interrupt Handler executed.

59. Conclusion

60. Exceptions are extraordinary situations that effect normal M68k operation. Exception Handling help M68k to:  Recover from errors.  Prioritize CPU tasks. M68k recognizes exceptions using VN.

61. Conclusion Exception handling involves:  Saving processor context.  Handling the exception.  Restore processor context.  Return to normal execution once exception is handled. Handles are instructions used to manage exceptions.  Located in SV memory location.

62. Exception Handler Operation TRAPV Save return address and flags on stack. Read handler address from Vector Table. Read return address and flags from stack. Save Registers Handler Code Reload Registers RTE

63. The End Please read: Antonakos, pg. 103-133.