1. Status – Week 274 Victor Moya

2. Simulator model Boxes. Boxes. Perform the actual work. Perform the actual work. A box can only access its own data, external data must come through signals (time!). A box can only access its own data, external data must come through signals (time!). The box manages its own signals. The box manages its own signals. A box: A box: whatever you do in 1+ cycle or whatever whatever you do in 1+ cycle or whatever or or what a piece of hardware does what a piece of hardware does

3. Simulator Model Signals. Signals. Communication between boxes. Communication between boxes. Carry the simulator time: 1+ cycle latency. Carry the simulator time: 1+ cycle latency. Parameters: bandwidth, latency. Parameters: bandwidth, latency. Storage size: bw * (lat + 1). Storage size: bw * (lat + 1). Not allowed read and write with latency 0. Not allowed read and write with latency 0.

4. Simulator Model Wiring boxes: Wiring boxes: Global static object. Global static object. Creates and binds signals by name. Creates and binds signals by name. Statistics Statistics Global static object. Global static object. Boxes declare a statistic name. Boxes declare a statistic name. The statistics object manages the different statitistics. The statistics object manages the different statitistics.

5. Simulator Model BOX Signal BOX SignalBinder StatisticBinder Signal Box Statistic

6. Simulator Model Box1 Box2 write read bw:2 lat: 3

7. Problems Must be 0 latency for wires forbidden? => NO! Must be 0 latency for wires forbidden? => NO! What happens if a two boxes must communicate in the same cycle? => NOT ALLOWED!. What happens if a two boxes must communicate in the same cycle? => NOT ALLOWED!.

8. Problems How to manage multiple instances of the same Box (4 vertex shaders, 8 pixel shaders). How to manage multiple instances of the same Box (4 vertex shaders, 8 pixel shaders). Create each instance as a different class with its own name and signal binding. Create each instance as a different class with its own name and signal binding. Box() now has a parameter Name that defines a different name for each instance (How can we grant the names are different?). Box() now has a parameter Name that defines a different name for each instance (How can we grant the names are different?). How to bind signals in multiple instanced boxed (VS, PS). How to bind signals in multiple instanced boxed (VS, PS). Signal are created/binded by the signal emiter and receiver. Signal are created/binded by the signal emiter and receiver. Prefix signal name with instance name. Prefix signal name with instance name. Add new parameters to Box() for the emiters name instances. Add new parameters to Box() for the emiters name instances.

9. Vertex Shader VS 1.0 (NV20) based Vertex Shader model. VS 1.0 (NV20) based Vertex Shader model. Multithread (multivertex?) supported. Multithread (multivertex?) supported. No branching. No branching. No texture/vertex buffer load. No texture/vertex buffer load. No vertex kill. No vertex kill.

10. Vertex Shader

11. VS 2.0+ (NV30) based Vertex Shader model. VS 2.0+ (NV30) based Vertex Shader model. Multithreaded?? Implemented with a FP array (3DLabs P10). Multithreaded?? Implemented with a FP array (3DLabs P10). Dynamic branching. Dynamic branching. No texture/vertx buffer load. No texture/vertx buffer load. No vertex kill. No vertex kill.

12. Vertex Shader

13. VS 3.0 (DX9.1). Not implemented yet. VS 3.0 (DX9.1). Not implemented yet. Hardware implementation unknown. Hardware implementation unknown. Static and dynamic branching. Static and dynamic branching. Texture/Vertex Buffer load (and store?). Texture/Vertex Buffer load (and store?). Possible vertex kill? Possible vertex kill?

14. Vertex Shader Model Instruction Fetch Instruction Fetch Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1). Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1). Decode/Register Decode/Register Calculates next PC (sequential, jump, conditional jump, calls, return, indirect) and sends it to Instruction Fetch (latency 1). Calculates next PC (sequential, jump, conditional jump, calls, return, indirect) and sends it to Instruction Fetch (latency 1). Reads up to three source operands from the register files (Vertex Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1). Reads up to three source operands from the register files (Vertex Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1). Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary). Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary). Execute Execute Performes an operation with the operands received with from the Decode/Register box and sends the result back to Decode/Register box with 1+ latency. Performes an operation with the operands received with from the Decode/Register box and sends the result back to Decode/Register box with 1+ latency.

15. Vertex Shader Model

16. DirectX 9 Almost ready. Almost ready. DX 9 RC 0 just released. DX 9 RC 0 just released. ATI DX9 demos and drivers. ATI DX9 demos and drivers. GDC Presentations are available already. GDC Presentations are available already. Introduction to VS/PS 3.0 and beyond. Introduction to VS/PS 3.0 and beyond.

17. NV30 Product ‘release’. Product ‘release’. Cards in February. Cards in February. Reviews in later December. Reviews in later December. 400-500 MHz. 400-500 MHz. 0.13 um, 125 M Transistors. 0.13 um, 125 M Transistors. FP array implements the vertex shader. FP array implements the vertex shader. 8 pixel pipes, 1 TMU. 8 pixel pipes, 1 TMU. 128bit 500 MHZ DDRII. 128bit 500 MHZ DDRII.