1. L2 Silicon Track Trigger All D0 Meeting 11 January 2002 Ulrich Heintz Boston University

2. 1/11/2002Ulrich Heintz - ADM2 People and Institutions Boston University –Ulrich Heintz, Meenakshi Narain –Evgeny Popkov, Lars Sonnenschein, Jodi Wittlin –Kevin Black, Sarosh Fatakia, Lorenzo Feligioni, Alex Zabi –Eric Hazen, Bill Earle, Shouxiang Wu Columbia University –Hal Evans –Georg Steinbrück –Tulika Bose –An Qi Florida State University –Horst Wahl, Sue Blessing, Stephen Linn, Harrison Prosper –Bill Lee, Sylvia Tentinto-Repond –Reginald Perry, Arvindh Lalam, Shweta Lolage SUNY Stony Brook –John Hobbs –Wendy Taylor –Huishi Dong –Chuck Pancake, Bonnie Smart, Jane Wu

3. 1/11/2002Ulrich Heintz - ADM3 STT Functionality Include SMT data in track trigger –Only available at level 2 –Use level 1 tracks as seeds for roads –Search for SMT hits in roads –Perform fit to SMT + CFT hits

4. 1/11/2002Ulrich Heintz - ADM4 Physics Motivation Improved p T resolution and impact parameter measurement

5. 1/11/2002Ulrich Heintz - ADM5 Physics Motivation Higgs Search –ZH  bb is almost as important as WH –For M H = 110 GeV Without STT:  = 35%  14 fb -1 for 3  With STT:  = 80%  10 fb -1 for 3  ProcessCross section Branching fraction SignalBackground WH  l bb 224 fb8.1%5.057 ZH  ll bb128 fb2.6%0.93.2 ZH  bb 128 fb15.4%4.656 Source: Fermilab SUSY/Higgs study

6. 1/11/2002Ulrich Heintz - ADM6 Physics Motivation Z  bb –requires two-jet trigger with low threshold –L2STT gives factor 13 rejection 50% efficiency –allows unprescaled Z  bb trigger –establish bb lineshape, efficiency H  bb search –b-jet scale to 1/3% stat Top mass measurement

7. 1/11/2002Ulrich Heintz - ADM7 D0 Trigger System L2FW:Combined objects (e, , j) L1FW: towers, tracks, correlations L1CAL L2STT Global L2 L2CFT L2PS L2Cal L1 CTT L2 Muon L1 Muon L1FPD Detector L1 TriggerL2 Trigger 7 MHz5-10 kHz CAL FPS CPS CFT SMT Muon FPD 1000 Hz

8. 1/11/2002Ulrich Heintz - ADM8 Conceptual Design L1CTT  tracks in CFT –Define road in SMT Select SMT hits in roads Fit trajectory to L1CTT+SMT hits. Measure –pT, –impact parameter, –azimuth Send results to L2 Pass L1CTT information to L2 Send SMT clusters to L3 road data SMT data Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Fiber Road Card Silicon Trigger Card Track Fit Card L2CTT

9. 1/11/2002Ulrich Heintz - ADM9 Motherboard 9Ux400mm VME board SCL mezzanine card (FRC) Up to 6 link boards Logic card Buffer controller Dedicated lines SCL  logic card VTM  logic card 3 PCI busses (32bit/33MHz) Link boards  logic card Buffer controller  logic card Universe II bridge PCI bus to VME bus Design complete

10. 1/11/2002Ulrich Heintz - ADM10 Motherboard

11. 1/11/2002Ulrich Heintz - ADM11 Link Transmitter/Receiver Boards PCMIP standard 3 LVDS serial links –24 bits @ 66 MHz –16 data bits –Single bit error correction –Multibit error detection –>10 12 bits w/o error 256k buffer (?) design complete

12. 1/11/2002Ulrich Heintz - ADM12 Fiber Road Card –SCL Receive 128 bits every 132 ns Fan out L1_QUAL, L1_TURN, L1_BX –L1CTT data Receive 1.5 Gbit/s glink  VTM Fan out –manage L3 buffers control allocation/deallocation of L3 buffers send readout requests to VBD send monitoring requests to CPU –arbitrate VME bus

13. 1/11/2002Ulrich Heintz - ADM13 FRC

14. 1/11/2002Ulrich Heintz - ADM14 Buffer Controller Universe II L3 Data Buffer Daughterboard Buffer Controller L3 Data Memory Output FIFO PCI-3 Input FIFO BM msg Inter- face L1 msg FIFO L2 msg FIFO BX Evt No. PCI Interface L3 Data Controller Data J3J3 L1_busy L1_error message DB_L3_RDY,BC_BUSY, L1/2_ERROR,L1/2_BUSY L2_error PCI Interface

15. 1/11/2002Ulrich Heintz - ADM15 FRC Buffer controller Buffer controller FRC

16. 1/11/2002Ulrich Heintz - ADM16 Silicon Trigger Card Strip reader Cluster finder Hit filter SMT L1CTT Road LUT SCL L3 TFC via serial link from FRC via serial link control logic 3131 3030 2929 2828 2727 2626 2525 2424 23232 2121 2020 1919 1818 171616 1515 1414 1313 1212 111010 9876543210 track dE dx sequencerHDIchipcentroid L3 channel logic (x8)

17. 1/11/2002Ulrich Heintz - ADM17 Processing of SMT Data bad strip mask –zero amplitude of flagged strips pedestal/gain calibration –chip-by-chip lookup table clustering algorithm –similar to offline, use 5 strips for centroid cluster centroid strip pulse height

18. 1/11/2002Ulrich Heintz - ADM18 STC Prototype 1 (2 channels) control logic control logic Road LUT Road LUT Xxxx xxxx Xxxx xxxx channel logic (Altera APEX) 1.5M gates 300 kbits RAM 652 pin BGA $1270 accommodates 2 channels  need 4/STC channel logic (Altera APEX) 1.5M gates 300 kbits RAM 652 pin BGA $1270 accommodates 2 channels  need 4/STC

19. 1/11/2002Ulrich Heintz - ADM19 STC Prototype 2 (8 channels) Road LUT Road LUT Road L UT Road L UT control logic (8x) channel logic (Xilinx Virtex E) 800k gates 1.1 Mbits RAM 560 pin BGA $1200 accommodates all 8 channels  need 1/STC Xilinx donated ¼ 70 FPGAs control logic (8x) channel logic (Xilinx Virtex E) 800k gates 1.1 Mbits RAM 560 pin BGA $1200 accommodates all 8 channels  need 1/STC Xilinx donated ¼ 70 FPGAs

20. 1/11/2002Ulrich Heintz - ADM20 Track Fit Card roads from FRC hits from STC tracks to L2 TI6202/3 (300 MHz)DSPs

21. 1/11/2002Ulrich Heintz - ADM21 Track Fit Algorithm require hits in –at least 3 of the 4 SMT layers –in same 30 degree sector –in at most 2 adjacent barrels choose hits –closest to trajectory defined by CFT and origin linearized  2 fit –  ( r) = b/r +  r +  0 –drop worst hit and refit if 4-hit  2 bad –measured execution time ¼10-15  s for a single pass road with 3-6 hits

22. 1/11/2002Ulrich Heintz - ADM22 TFC

23. 1/11/2002Ulrich Heintz - ADM23 Hotlink Transmitter Transmits data from TFC to MBT in L2CTT –cypress hotlink –8 bits @ 16 MHz –no errors in 5£10 12 bits transferred to MBT using built-in self test

24. 1/11/2002Ulrich Heintz - ADM24 L2STT Crate LVDS serial links for communication between boards

25. 1/11/2002Ulrich Heintz - ADM25 Inventory moduleFRCSTCTFCCrateTotal FRC logic board1--16 STC logic board-1-954 TFC logic board--1212 motherboard1111272 SCL mezzanine card1--16 link transmitter41-1378 link receiver-131590 hotlink transmitter--1212 buffer controller1111272 VTM11-1060

26. 1/11/2002Ulrich Heintz - ADM26 MCH2 Passive Splitters in MCH2 –split g-link fiber from sequencer into two paths: STT and VRB Racks M202, M203, M204 in MCH2 M202-204

27. 1/11/2002Ulrich Heintz - ADM27 Output to L2CTT –all data from L1CTT –for each track 012345678910111213141516171819202122232425262728293031 pTpT ±S 22 xxf bxdE/dxtrackxxffffbarrelf pTpT transverse momentum encoded in 0.25(3) GeV increments for p T ) 25 GeV: bimpact parameter dE/dxionization ±signtracktrack number (0-45) Simpact parameter significancebarrelbarrel number  azimuthftopology flags 22 goodness of fitxspares

28. 1/11/2002Ulrich Heintz - ADM28 Output to L3 for each event –all information sent to L2CTT –for all SMT clusters –for all SMT clusters associated with a track 313029282726252423222120191817161514131211109876543210 0chantyp dE dx sequencerHDIchipcentroid 313029282726252423222120191817161514131211109876543210 track dE dx sequencerHDIchipcentroid

29. 1/11/2002Ulrich Heintz - ADM29 Beam Stability Need: –<500  m offset, stable to <30  m –<100  rad tilt Vertex package in EXAMINE –Measure beam trajectory during run –Download at beginning of run –Store in accelerator control system –Input to feedback system

30. 1/11/2002Ulrich Heintz - ADM30 System Test BU –Test vectors –FRC  STC  TFC FNAL –Integrate FRC and SCL/L1CTT STC and SMT –Vertical slice next

31. 1/11/2002Ulrich Heintz - ADM31 Schedule as of October 2001: –System Test mid December 2001 – mid January 2002 –Production mid January – mid May 2002 –Installation/Commissioning mid May – mid June 2002.... about 1 month late due to delays in prototype testing

32. 1/11/2002Ulrich Heintz - ADM32 Run 2b SMT replacement: 6 axial barrel layers –more readout units (HDIs) –need more STC boards no upgradefull upgrademodest upgrade

33. 1/11/2002Ulrich Heintz - ADM33 Run 2b Option No upgrade Modest upgrade Full upgrade FRC logic board666 STC logic board546072 TFC logic board12 motherboard727890 SCL mezzanine card666 link transmitter7890102 link receiver9096108 hotlink transmitter12 buffer controller727890 VTM606678 Additional cost (no cont.)$34k$81k$231k

34. 1/11/2002Ulrich Heintz - ADM34 Conclusions All modules prototyped Integration tests under way Production –started for some boards –rest will follow after more tests (¼ Feb) Goal: operational in June 2002 Documentation –http://www-d0.fnal.gov/~wahl/vtxt.html