1. Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Basic Component Simulation 02/25/2004 Current Stage: Basic Component Simulation 02/25/2004 Design Manager: Rebecca Miller

2. Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout (100% done) Basic components Basic components  To be done Program of control signals for architecture modification Program of control signals for architecture modification Layout of larger blocks Layout of larger blocks Component Simulation Component Simulation Top-Level layout routing Top-Level layout routing Barrel shifter spice simulation Barrel shifter spice simulation

3. Updated 48’b XOR Rise Time Old: 3.169n New: 840p

4. Updated 48’b XOR Fall Time Old: 1.401n New: 282p

5. Updated 48’b XOR Prop Time Old: 628.762p New: 253.7p

6. Permutation Rise Time Old: 1.367n New: 276.6p

7. Permutation Fall Time Old: 619.931p New: 182.8p

8. Permutation Propagation Time Old: 1.03p New: 419p

9. Project Goals Implement fully functioning 3DES Chip. Implement fully functioning 3DES Chip. 300Mhz speed. CPU speeds in current ATMS range from 400-600Mhz. 300Mhz speed. CPU speeds in current ATMS range from 400-600Mhz. Dense design for small area in existing machines. Dense design for small area in existing machines.

10. Critical Path Estimate Mux: 288.811p TextBox: 911.5p Mux: 288.711p EXP: 419p XOR: 253.7p SBOX: 552.382p P: 419p XOR: 253.7p ----------------------- Total: 3.386n SPEED 295.3Mhz Old SPEED 168Mhz

11. Design Decisions Permutation Optimization

12. Updated Architecture KeyReg 56’b Register 32’b 32’b input IP -1 wiring PC-2 Wiring 56->48 IP wiring Text 64’b Register Expand 32->48 wiring S-Box 512 x 4’b P 32->32 wiring PC (wiring) 32’b Latch 2:1 mux Sub_rnd txt_in ready key_in 32 64 32 “R” “L” R L 56 48 32 wr_en OUT ready 32 2:1 mux 32 64 2:1mux 32’b Latch 2:1 mux Sub_rnd Enc_ShiftL Dec_ShiftR 2:1 mux Sh_d Sh_e e/d Enc_ShiftL Dec_ShiftR Sh_d Sh_e

13. Floorplan Floorplan 32’b Latch PC1 Right Barrel Shifter 56’b Mux 56’b Key Reg PC2 IP Mux IP-1 32’b Text Register (L) 32’b Text Register (R) 32’b Mux 32’b XOR Expand 48’b XOR P SBOX 32’b Mux All large functional blocks use Metal 1 and Metal 2. M1 M2 M3 M4 Input Mux Output Program Control clock 416μm 360μm Left Barrel Shifter 56’b

14. Floorplan Floorplan Input Latch Initial Permutation Barrel Shifting Key Register Barrel Shifting Initial Permutation Final Permutation Key Register XOR Expand Permutation P Permutation S BOX ROM and Decoders Program Control Transistors: 15014 Area: 415.9μm x 366.8 μm

15. Metal1 Metal1

16. Metal2 Metal2

17. Metal3 Metal3

18. Poly Poly

19. Transistors Transistors

20. Problems and Issues  XOR Rise/Fall times have significant difference Performance not impacted by W/L Ratio Performance not impacted by W/L Ratio Increasing size reduces resistance Increasing size reduces resistance Offset by an increase in diffusion capacitance Offset by an increase in diffusion capacitance  Buffer control signals to traverse chip

21. Questions ?