1. DSP Architecture Differences and Examples of Embedded Computers Lecture 3 January 18, EENG 449b / CPSC 439b Computer Systems
Andreas Savvides
Office: AKW 212
Tel
Course Website

2. Recap: 5 Steps of MIPS Datapath
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back
Next PC
MUX 4
Adder
Next SEQ PC
Zero?
RS1
Reg File
Address
MUX
Memory
RS2
ALU
Inst
Memory
Data L M D RD
MUX
MUX
Sign
Extend
Imm
WB Data

3. How do DSP Processors Differ?
Designed for high performance, repetitive numerical intensive tasks
Distinct features:
Single cycle multiply accumulated instructions (MAC)
Useful for digital filters, FFTs, correlation computations
Several memory accesses in the same cycle
One or more address generation units

4. An example DSP processor datapath

5. Specialized Addressing Modes
Register indirect addressing with post increment
In MIPs we have add R4, (R1)
How would it be in DSP?
Modulo addressing
Bit-reverse addressing => FFT
FFTs algorithms shuffle their addressing
Eg 0,1,2,3,4,5 is accessed 0,4,2,6,1,5

6. Specialized I/O Handling Mechanisms
DSPs need to get a lot of data from outside world
Cameras, celphones, MP3 Players
Acquire data w/o processor interruption
Specialized interrupt schemes
DMA transfer units, specialized serial and parallel ports
Mutliport memories and independent memory banks
Multiple on chip buses
Tools disadvantages: general purpose processors have more tools available.

7. DSP Design Choices Arithmetic format
Fixed Point vs. Floating Point
Fixed point: numbers are integers or fractions in fixed range
Floating point:
Exponent and mantissa
Mantissa x 2exponent
Fixed vs. floating point tradeoffs?

8. DSP Data Widths & Speed Floating point; mostly 32-bit
Fixed point: 16-bit
Speed factor:
Clock speed does not tell the whole story
MIPS is the common metric
Some DSPs use a VLIW architecture

9. Harvard vs. Von Neumann

10. Software Development Path

11. An Example Microcontroller OKI ML67Q5002 (Not a DSP!)
32-bit ARM7TDMI core (16-bit THUMB mode)
Built-in memory:
SRAM 32Kbytes
Boot ROM 4Kbytes
FLASH memory 256Kbytes
Provided interfaces:
4 channels of 10-bit resolution ADC.
DMA support.
SPI, SIO, I2C, UART, PWM interfaces
42 configurable GPIO pins
Variety of external and internal configurable interrupts
6 hardware timers

12. XYZ Computation: The OKI ARM ML675001/67Q5002/67Q5003
Features
ARM7TDMI
ROM-less (ML675001)
256KB MCP Flash (ML67Q5002)
512KB MCP Flash (ML67Q5003)
8KB Unified Cache
32KB RAM
Interrupts FIQ
I2C (1-ch x master)
DMA (2-ch)
Timers (7 x 16-bit)
WDT (16-bit)
PWM (2 x 16-bit)
UART (2-ch)/ SIO (1-ch)
GPIO (5 x 8-bit)
ADC (4-ch x 10-bit)
up to 66MHz
-40 ~ +85 C
Package 144 LFBGA
144 QFP
[Slide from OKI Semiconductor]

13. OKI ARM ML675001/67Q5002/67Q5003
ARM7TDMI

14. What does ARM7TDMI Mean? Based on an ARM7 core Von Neuman Architecture
Same address and data bus
Approximately 1.9 Clock cycles per instruction
T – Thumb architecture extension – 2 instruction sets
ARM 32-bits
Thumb 16-bits
D – Core has debug extensions
M – Core had an enhanced multiplier (32x8) with instructions for 64-bit results
I – Core has EmbeddedICE Logic Extensions

15. CPU States CPU can be either in ARM or THUMB states
User can implicitly change the processor state from ARM to THUMB
All exception handling happens in ARM mode
If an exception happens during Thumb mode, the the processor transitions to ARM to execute the instruction and returns to THUMB at the end of the exception handler
THUMB mode trades-off performance for code density
Cheaper memory and lower power consumption for embedded systems

16. External SRAM
starts here
Internal RAM
starts here
FLASH Starts here

17. MCU Basics: What are interrupts?
Asynchronous breaks in the program execution
Press of a button, expiration of a timer, DMA interrupt indicating the completion of a memory transfer
When an interrupt occurs, the processor will transition to the corresponding interrupt handler to service the interrupt and then resume execution
The OKI processor has an 8-level interrupt priority mechanism
Total of 24 types of interrupts that can happen during instruction execution
1 fast external interrupt
4 external interrupts
19 Internal interrupts
E.g System timer, watchdog timer, DMA interrupts etc
The chip has mechanisms for dealing with interrupts
Interrupts are enabled and disabled through registers for each peripheral

18. Hardware Timers(16-bit)
Holds the value that initializes the timer at
startup
Holds value to compare against
Controls the mode (interval or one-shot)
Starts and stops the timer
Enables/disables the interrutps for this timer

19. Clock Divider

20. Steps in Setting up a Hardware Timer
Example using hardware TIMER0
Stop timer & disable interrupts by writing to control register (TIMECNTL0)
Write the timer starting value to the base register (TIMEBASE0)
Write the stop value in the compare register (TIMECOMP0)
Start the timer by writing to the control register (TIMECNTL0)
This will start the timer. An interrupt will occur when the counter register reaches the value of the compare register
Note: After the interrupt is handled, the status register (TIMESTAT0)needs to be cleared to use the timer again.

21. How to you access peripherals?
You can access peripherals and GPIO by reading/writing registers
Typically one would write device drivers and then use higher level abstractions
You will need this knowledge to write device drivers for different peripherals and to assess the real-time capabilities of your software

22. Some platforms & applications
Seismic monitoring, personal exploration rover, mobile micro-servers, networked info-mechanical systems, hierarchical wireless sensor networks
[Intel + UCLA]
[NIMS, UCLA]
[Robotics, CMU]
[CENS, UCLA]
[Intel + UCLA]
[Slide from V. Ragunanthan]

23. A Generic Sensor Node Architecture
PROCESSING
SUB-SYSTEM
COMMUNICATION
SENSING
POWER MGMT.
ACTUATION

24. Base Case: The Mica Mote (The most popular sensing platform today)
51-PIN I/O Connector
Digital I/O
Analog I/O
Programming
Lines
AVR 128, 8-bit MCU
DS2401
Unique ID
Co-processor
Transmission
Power Control
Hardware
Accelerators
External Flash
Radio Transceiver
(CC1000 or CC2420)
Power Regulation MAX1678(3V)
For more information refer to the TinyOS Website

25. What is Stargate? A single board, wireless-equipped computing platform
Developed at Intel Research
Leverages advances in computation, communication and storage to facilitate wireless systems research

26. System architecture

27. Computation sub-system
PXA255 processor based on the XScale microarch.
Successor to the StrongARM family
Variable clock ( MHz), less than 500 mW power
Several sleep modes, rich set of peripherals

28. Wireless DPM: Hierarchical radios
Three vastly different wireless radios supported
Combined to form power-efficient, heterogeneous communication subsystem
Hierarchical device discovery and connection setup scheme leads to up to 40X savings in discovery power
Mote
Bluetooth
Energy per bit
Startup time
Idle current
IEEE
Startup cost -> startup time
Technology
Data Rate
Tx Current
Energy per bit
Idle Current
Startup time
Mote
76.8 Kbps
10 mA
430 nJ/bit
7 mA
Low
Bluetooth
1 Mbps
45 mA
149 nJ/bit
22 mA
Medium
802.11
11 Mbps
300 mA
90 nJ/bit
160 mA
High

29. Other power management features
Wake on wireless: Bluetooth based remote wakeup
BT module awake, rest of the system is shutdown
Incoming BT packet causes wakeup
On-demand power management (event-driven apps)
BT module in “wake on wireless” mode draws ~ 3mA
Motion detection for wake up
Passive small-bead mercury switch connected to GPIO
Movement causes switch to close and wakeup system
Can also be used to trigger wireless scanning for APs

30. UCLA iBadge

31. iBadge Functional Units
Main Processing Unit
ATMega128L Microcontroller from Atmel
Responsible for power management, localization, and interfaces different functional units
Localization Unit:
Relative and absolute positioning
responsible for obtaining precise 3D location of iBadge in the classroom
estimates its 3D location using an ad-hoc localization process
Speech Processing Unit:
Consists of TI DSP and CODEC
Performs speech codec and front end processing of the real time speech of the children
Two modes (Simple Coding or Front End Processing) of operation based on power requirements and user request.

32. iBadge Functional Units (Continued)
Power Management/Tracking Unit:
Battery Monitors (DS2438) keep track of energy usage of various functional units
CMOS switches provides control to turn on/off different part of the circuits
Orientation/Tilt Sensing Unit
Accelerometer combined with magnetometer provides the orientation of the children with earth’s magnetic field
Environment Sensing Unit
Temperature, Humidity, Atmospheric Pressure, and Light Intensity

33. Telos: New OEP Mote* Single board philosophy
Robustness, Ease of use, Lower Cost
Integrated Humidity & Temperature sensor
First platform to use
CC2420 radio, 2.4 GHz, 250 kbps (12x mica2)
3x RX power consumption of CC1000, 1/3 turn on time
Same TX power as CC1000
Motorola HCS08 processor
Lower power consumption, 1.8V operation, faster wakeup time
40 MHz CPU clock, 4K RAM
Package
Integrated onboard antenna +3dBi gain
Removed 51-pin connector
Everything USB & Ethernet based
2/3 A or 2 AA batteries
Weatherproof packaging
Support in upcoming TinyOS Release
Codesigned by UC Berkeley and Intel Research
Available February from Moteiv (moteiv.com)
*D. Culler, UC Berkeley

34. Yale’s XYZ Sensor Node Sensor node created for experimentation
Low cost, low power, many peripherals
Integrated accelerometer, light and temperature sensor
Uses an IEEE protocol
Chipcon 2420 radio
OKI ARM Thumb Processor
256KB FLASH, 32KB RAM
Max clock speed 58MHz, scales down to 2MHz
Multiple power management functions
Powered with 3AA batteries & has external connectors for attaching peripheral boards
Designed at Yale Enalab and Cogent computer systems, will be used as the main platform for the course

35. XYZ’s Architecture

36. XYZ: Communication Subsystem
Chipcon CC2420 Zigbee RF Transceiver
2.4 GHz IEEE 250Kbps
Programmable output power
RX/TX data buffering
Digital RSSI support
DSSS modulation
Security features
CTR encryption/decryption
CBC-MAC authentication
CCM encryption and authentication
All security operations are based on AES encryption using 128 bits

37. XYZ: Supervisor Circuitry & Low Power Sleep
OKI μC
Voltage Regulator
3.3V
Enable
Interrupt (SQW)
WAKEUP
3 x AA batteries
RTC
DS1337
I2C
Step 1: The μC selects the total time that wants to be turned off and programs the DS1337 accordingly, through the 2-wire serial interface.
Step 2: The DS1337 turns-off the μC and uses its own crystal to keep the notion of time.
Step 3: The DS1337 wakes up the μC after the programmed amount of time has elapsed.
Note that the DS1337 RTC can disable the voltage regulator and completely turn-off the sensor node!
DS1337 Real Time clock datasheet:

38. XYZ: On Board Sensors Light Accelerometer OKI μC Temperature A D C
AIN0
OKI μC A D C
Accelerometer X
AIN1 Y
AIN2
Temperature
PIOE5(EXINT0)
Light Sensor datasheet (TSL251R):
Temperature Sensor datasheet (TMP05):
2-axis accelerometer datasheet (ADXL202E):

39. Current Efforts on XYZ Peripheral Boards
UCLA
Suspended nodes and camera Yale, ENALAB

40. Manufacturers of Microcontroller Based Sensor Nodes
Millenial Net (
iBean sensor nodes
Ember (
Integrated IEEE stack and radio on a single chip
Crossbow (
Mica2 mote, Micaz, Dot mote and Stargate Platform
Intel Research
Stargate, iMote
Dust Inc
Smart Dust
Cogent Computer (
XYZ Node (CSB502) in collaboration with
Mote iv – Telos Mote
Sensoria Corporation (
WINS NG Nodes
More….

41. Other Sensor Node Projects
Augmented off-the-shelf systems
PC104 computers (used in some habitat monitoring applications)
iPAQ PDAs (used for UCLA/CENS)
Networked Infomechanical Systems (NIMS)
Dedicated embedded sensor nodes and SOCs
MIT uAMP nodes (
Berkeley BWRC picoradio node (
ISI Pasta node (

42. Typical Operating Characteristics for 4 classes of Sensor Nodes
Source: J. Hill, M. Horton, R. King and L. Krishnamurthy,”The Platforms Enabling Wireless Sensor
Networks”, Communications of the ACM June 2004

43. Power Perspective Comparison of Energy Sources
With aggressive energy management, ENS might
live off the environment.
Source: UC Berkeley & CENS

44. Many ways to Optimize Power Consumption
Power aware computing
Ultra-low power microcontrollers
Dynamic power management HW
Dynamic voltage scaling (e.g Intel’s PXA, Transmeta’s Crusoe)
Components that switch off after some idle time
Energy aware software
Power aware OS: dim displays, sleep on idle times, power aware scheduling
Power management of radios
Sometimes listen overhead larger than transmit overhead
Energy aware packet forwarding
Radio automatically forwards packets at a lower level, while the rest of the node is asleep
Energy aware wireless communication
Exploit performance energy tradeoffs of the communication subsystem, better neighbor coordination, choice of modulation schemes