1. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 13 Direct Memory Access (DMA)

2. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter Objectives Review and compare main types of I/O Introduce Direct Memory Access (DMA) I/O Explain basic DMA operation: HOLD, HLDA Introduce the 8237A programmable DMA controller (DMAC) Describe various types, modes and applications of DMA data transfer

3. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Review of I/O Types 1. Programmed I/O I/O between memory and the I/O device is performed by the Processor: e.g. IN AL,DX MOV [DI],AL; Transfer is through the  P - slow! 1.1 Polling/Handshaking I/O Processor checks device readiness repeatedly, e.g. in a tight loop 1.2 Interrupt-driven I/O Device signals its readiness by an interrupt. Processor performs I/O by executing an ISR. Otherwise processor is doing other useful work 2. Direct Memory Access (DMA) - Avoids the slow speed of programmed I/O when moving large amounts of data between memory and a peripheral - Data transfer is coordinated by a DMA controller- not the processor - Avoids the bottleneck of having to channel data through the  P - Uses the 3  P buses, so the  P is unable to use them temporarily - Speed is limited only by those of the memory and the DMAC

4. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Direct Memory Access (DMA) is a method whereby the memory and I/O space of the microprocessor can be accessed directly without the intervention of the microprocessor or a program. To request DMA access, the DMAC raises the HOLD input high. The microprocessor responds by floating the 3 buses and raising HLDA high to indicate that a hold is in effect. The DMAC can now use the 3 buses to do DMA transfers on them- bypassing the processor

5. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e During a HOLD, the microprocessor stops running the program and places its address, data, and control bus connections at their HiZ state. This in effect is the same as removing the microprocessor from its socket! While the microprocessor is held, other devices are free to gain access to its memory and I/O space and transfer data directly using them Usually this requires the use of a programmable DMAC chip: (Direct Memory Access Controller), e.g. the 8237A

6. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e HOLD is sampled during instruction execution while interrupt signals are sampled at the end of instructions HOLD takes effect (HLDA generated) in a clock cycle or two  So, Hold has a higher priority than interrupts The only input with a higher priority than HOLD is the RESET input to the microprocessor. Device Requests DMA Transfer DMA Request Granted-  P has relinquished control of the buses I/P O/P DMA finished

7. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Applications Wherever large amounts of data need to be transferred fast between memory and an I/O peripheral device, e.g. - Hard disk, CD - Video memory to refresh display - Sound cards - Network cards - Data acquisition boards Also for row address generation by hardware to refresh large DRAMs fast

8. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Memory Read I/O Write Simultaneously ! Memory address Generated by fast Counters on the DMAC C HOLD

9. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Control Signals Because during a DMA both memory and an I/O device may be accessed simultaneously, the DMAC may need to generate: - #MRDC and #IOWC (simultaneously) for memory to I/O device transfers - #IORC and #MRWC (simultaneously) for I/O device to memory transfers This was not necessary with programmed I/O as processor either accessed memory or an I/O device at any given time moving data between it and the processor

10. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DMAC Interface The DMAC is a Programmable I/O device for the microprocessor, Just like the PPI, PIC, UART, … DMA activities by the DMAC will be programmed into it by the processor before hand With HLDA Active Two types of DMA data transfers: 1. Sequential DMA: Read then Write through the DMAC Data rests in DMAC. Only M or IO controls are needed at any given time 2. Simultaneous DMA: Data moved directly between peripheral and memory. Both M & IO controls used at the same time

11. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The 8237A Programmable DMAC Four separate prioritized DMA channels (expandable by using multiple DMACs) Transfer rates up to 1.6 M bytes/s DMA transfers by the DMA channels are programmed a priori into the DMAC by the processor Can address 64KB of memory in one programming operation  16-bit addresses Allows the following DMA transfer combinations: -Memory to peripheral -Peripheral to memory -Peripheral to peripheral -Memory to memory No longer used on the PC in chip form nowadays- its functionality has been embedded into modern chip set ICs On-chip Address I/Ps  16 I/O adrs (Programming) DMA Device PP For address Counters - Data Bus (during Programng) - A8-A15 During DMA Address bus (during DMA)

12. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming the DMAC (Only these 3 numbers are written into the DMAC)

13. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Modes: Byte, Burst & Block (3 Bees!) Byte: Un-buffered device Burst: (a buffer-full of data) Fill the buffer of a slow device once Block: (multiple buffers) Fill the buffer of a fast Device several times DMAC gets more greedy for bus control Block finished? As long As Device Is Ready (filling its buffer) Only for a byte As long as needed to transfer the block (buffer full) Bars show duration of DMAC controlling the buses

14. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Comparison between the three types of I/O TypeAdvantagesDisadvantages Polling -Fastest response to device request -Simplest hardware and software - Wasted processor resources (always waiting) Interrupts - More efficient use of processor time (Processor executes program- checks for interrupts only at the end of every instructions) - Delay in response time (interrupt latency) -Overhead due to interrupt processing, e.g. saving return address & registers, context switching - Increased cost and complexity of hardware and software DMA -Fastest data transfer rates (approaching those determined by memory access time) Address generation by fast DMAC hardware- not by processor software -Need a DMAC device -Highest cost and complexity in hardware and software