# LAB 3 – Review of the Assignment. -- Clarifications Vikram Murali. TA : CSE 140L Prof. CK Cheng.

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LAB 3 – Review of the Assignment. -- Clarifications Vikram Murali. TA : CSE 140L Prof. CK Cheng.

Part 1.. FSM Traffic Light Controller. Designing an FSM for a simple signal system NS and EW signals NS = Green. EW = Red -> Default State

Part 1 Contd.. Walk NS and Walk EW  Input Signals. Walk EW = ON, Walk NS = Off, system changes from default state EW = Red, NS = Yellow  Orange  Red. When NS = Red, EW immediately turns green. Holds for two clock cycles. Then if Walk EW = 1, stays here. Else

Part 1 Contd.. NS = Red, EW = Yellow  Orange  Red. When EW = Red, NS immediately turns green. We have reached the default state.

Part 1.. Demonstration Implement the state machine, and then show how the signals change around for different input signals (i.e. Walk Signals) Be sure you can explain the transitions. This state machine is quite simple anyways.

Part 1.. Report - Draw the FSM of your traffic light controller (Moore). - Include the state/output table of your traffic light controller - Include schematic diagrams of your circuit - No need to include functional and timing diagrams. - Pretend your system is currently NS = green and EW = red. Someone comes along and presses the EW button. Then someone presses the NS button one second later. Describe what you see and explain why. Can you make the green light on EW hold forever? Explain.

Part 2.. The Train.

Part 2.. Contd.. Inputs : S1, S2, S3, S4. -- Sx = 0 => train far, -- Sx = 1 => train near. Outputs : SW 1, SW 2, Dir A, Dir B. -- SW 1 and SW 2 : switch controls -- SW1=SW2=0  Shared track connected to track A, else track B. -- Dir A and Dir B : control train motion. -- whether or not it happens. -- and in what direction. -- Dir A or Dir B = 00 => Stop. -- Dir A or Dir B = 10 => Causes the train in that direction to GO. -- Dir A or Dir B = 01 => Causes trains to Reverse.

Part 2.. Contd.. The train’s destiny is in your hands. Well, yes : the state transitions, outputs. -- You have to do it based on the problem statement, That’s the assignment ! RECAP : 4 I/Ps, 4 O/Ps, Problem statement. State transitions ? O/Ps ? Ensure the trains don’t collide.

Part 2.. Report. - Draw the FSM of your train controller - Include the VHDL code of your train - Write a 1/2 page (more if you want) description of what your VHDL code is doing for tcontrol. Start from the top and go towards the end. Convince us that you know what each major segment of the VHDL is doing. As we already know, the major segments are the ENTITY part, the ARCHITECTURE PART, the "PROCESS (clock) part", and the "WITH state SELECT" part. (This must be easy as Each of these was already discussed in detail in the discussion class). Relate the FSM with the VHDL code by explaining how the VHDL implements the FSM you came up with. -Let's have some fun with our train. Switch 1 and 2 are set incorrectly so that the incoming trains will derail. Try it! Describe what happens.

Part 2.. Bonus Points. Demonstrate some wacky or interesting train pattern. Vary the speeds or change the outputs, states, etc. See what you can do! Make the trains go in the reverse directions. Try : reversing Train B onto A and seeing what happens, or doing head-on collisions, etc. You can get B onto A's track or vice versa, or you can do funny train patterns. Have fun and be creative!! Your states might no longer make sense, such as the case when both A and B are on the same track, and one of the trains hits a sensor. You can fix this by adding the correct states, or you can try varying the speeds so that one train goes way faster than the other, ends up on the same track, and then rams the other train (before your train controller realizing something is wrong and freezing your trains). This one is for you guys to have fun and try various things, so don't worry about making a system that actually is correct!. It is fine if the trains are still no longer running on the tracks. But try to explain to us what is happening.

Part 2.. Demonstration Show that the trains run collision free on their tracks (on the monitor). Test the setup by varying SW 1,2,3 and 4 to control the speeds of the trains. (SW here means switches on the board). Why ? This will bring out any mistakes you may have committed in your state machines.

Part 3.. Sequence Detector. Design a simple sequence detector to output a 1 whenever a combination of 0110 is encountered in the input sequence. Give your inputs using push button switches and implement this problem statement as both Mealy and Moore machines in VHDL. Since you already know the framework, we are not going to give you any files here. So again : You need to make your state machines for both Mealy and Moore models for this detector, implement them in VHDL (Verilog also very much acceptable) and run it on Quartus, program it on your board and show us that and how it works.

Part 3.. Demonstration Just show a 1 (on one of the LEDs may be) when a 0110 is input using push button switches. Remember our clock is 1 hz. Period = 1second. Can use an input vector in your VHDL file if you find timing the presses of the push buttons weird. Can you detect other input sequences (say a 101) ? (This is not a requirement. But those who are on for an early finish might want to try.

Part 3..Report. - Your Mealy and Moore state machines. - Include your State transition tables. - VHDL/Verilog code for the sequence detector (both Mealy and Moore). - Mention the differences observed between the two models. Which do you think is better and why ? Explain. - Design the circuit using logic mininisation method. Get the final implementation on paper {like problem 1.} No need to use the board! Now compare both methods. Do you see how much more comfortable using HDL is ?

Deadlines Due : 19 th November 2010. Demonstration : Again using sign up sheets. Keep checking the class webpage : “News and Updates column” for more details.

Thank You again ! ……You were great listeners.

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