1. CS 61C L29 Combinational Logic Blocks (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 29 – Combinational Logic Blocks 2004-04-05 USF “Flashmob 1”   supercomputer effort! On Sat, organizers tried to create a supercomputer by harnessing 500 laptops together & run Linpack, a speed benchmark. Didn’t work. www.nytimes.com/2004/04/05/technology/05super.html

2. CS 61C L29 Combinational Logic Blocks (2) Garcia, Spring 2004 © UCB Review Use this table and techniques we learned to transform from 1 to another

3. CS 61C L29 Combinational Logic Blocks (3) Garcia, Spring 2004 © UCB A. B. N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND…TRUE Let’s verify! CORRECT 3-input XYZ|AND|OR|XOR|NAND 000| 0 |0 | 0 | 1 001| 0 |1 | 1 | 1 010| 0 |1 | 1 | 1 011| 0 |1 | 0 | 1 100| 0 |1 | 1 | 1 101| 0 |1 | 0 | 1 110| 0 |1 | 0 | 1 111| 1 |1 | 1 | 0 CORRECT 2-input YZ|AND|OR|XOR|NAND 00| 0 |0 | 0 | 1 01| 0 |1 | 1 | 1 10| 0 |1 | 1 | 1 11| 1 |1 | 0 | 0 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 …it’s actually FALSE Peer Instruction Correction

4. CS 61C L29 Combinational Logic Blocks (4) Garcia, Spring 2004 © UCB Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor

5. CS 61C L29 Combinational Logic Blocks (5) Garcia, Spring 2004 © UCB Data Multiplexor (here 2-to-1, n-bit-wide) “mux”

6. CS 61C L29 Combinational Logic Blocks (6) Garcia, Spring 2004 © UCB N instances of 1-bit-wide mux How many rows in TT?

7. CS 61C L29 Combinational Logic Blocks (7) Garcia, Spring 2004 © UCB How do we build a 1-bit-wide mux?

8. CS 61C L29 Combinational Logic Blocks (8) Garcia, Spring 2004 © UCB 4-to-1 Multiplexor? How many rows in TT?

9. CS 61C L29 Combinational Logic Blocks (9) Garcia, Spring 2004 © UCB Is there any other way to do it? Hint: NCAA tourney! Ans: Hierarchically!

10. CS 61C L29 Combinational Logic Blocks (10) Garcia, Spring 2004 © UCB Administrivia HW4 grading done; deadline in 1 week.

11. CS 61C L29 Combinational Logic Blocks (11) Garcia, Spring 2004 © UCB Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU) We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR

12. CS 61C L29 Combinational Logic Blocks (12) Garcia, Spring 2004 © UCB Our simple ALU

13. CS 61C L29 Combinational Logic Blocks (13) Garcia, Spring 2004 © UCB Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we’ve seen before Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer

14. CS 61C L29 Combinational Logic Blocks (14) Garcia, Spring 2004 © UCB Adder/Subtracter – One-bit adder LSB…

15. CS 61C L29 Combinational Logic Blocks (15) Garcia, Spring 2004 © UCB Adder/Subtracter – One-bit adder (1/2)…

16. CS 61C L29 Combinational Logic Blocks (16) Garcia, Spring 2004 © UCB Adder/Subtracter – One-bit adder (2/2)…

17. CS 61C L29 Combinational Logic Blocks (17) Garcia, Spring 2004 © UCB N 1-bit adders  1 N-bit adder What about overflow? Overflow = c n ? +++

18. CS 61C L29 Combinational Logic Blocks (18) Garcia, Spring 2004 © UCB What about overflow? Consider a 2-bit signed # & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Highest adder C 1 = Carry-in = C in, C 2 = Carry-out = C out No C out or C in  NO overflow! C in, and C out  NO overflow! C in, but no C out  A,B both > 0, overflow! C out, but no C in  A,B both < 0, overflow! ± # What op?

19. CS 61C L29 Combinational Logic Blocks (19) Garcia, Spring 2004 © UCB Lecture ended on the previous slide

20. CS 61C L29 Combinational Logic Blocks (20) Garcia, Spring 2004 © UCB What about overflow? Consider a 2-bit signed # & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Overflows when… C in, but no C out  A,B both > 0, overflow! C out, but no C in  A,B both < 0, overflow! ± #

21. CS 61C L29 Combinational Logic Blocks (21) Garcia, Spring 2004 © UCB Extremely Clever Subtractor

22. CS 61C L29 Combinational Logic Blocks (22) Garcia, Spring 2004 © UCB Peer Instruction A. Truth table for mux with 4-bits of signals is 2 4 rows long B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

23. CS 61C L29 Combinational Logic Blocks (23) Garcia, Spring 2004 © UCB “And In conclusion…” Use muxes to select among input S input bits selects 2S inputs Each input can be n-bits wide, indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1- bit adders with XOR gates on input XOR serves as conditional inverter