# 1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego.

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1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego

2 Part III - Standard Combinational Modules Decoder: Decode address Encoder: Encode address Multiplexer (Mux): Select data by address Demultiplexier (DeMux): Direct data by address Shifter: Shift bit location Adder: Add two binary numbers Multiplier: Multiply two binary numbers

3 Interconnect: Decoder, Encoder, Mux, DeMux P1 Memory Bank Mux, P2 Pk Demux Decoder Mux Data Address Address k Address 2 Address 1 Data 1 Data k Arbiter n n-m m2m2m

4 1. Decoder Definition Logic Diagram Application (Universal Set) Tree of Decoders

5 1. Decoder: Definition 0 y0y1y7y0y1y7 I0I0 I1I1 I2I2 1 2 0123456701234567 EN (enable) n inputs n= 3 2 n outputs 2 3 = 8 y i = 1 if En= 1 & (I 2, I 1, I 0 ) = i y i = 0 otherwise n to 2 n decoder function:....

6 N inputs, 2 N outputs One-hot outputs: only one output HIGH at once 1. Decoder: Definition

7 Decoder: Logic Diagram y0y0 I2’I2’ I1’I1’ I0’I0’ y1y1 I2I2 I1’I1’ I0’I0’ En y7y7 I2I2 I1I1 I0I0.... y i = m i En y 0 = 1 if (I 2, I 1, I 0 ) = (0,0,0) & En = 1 y 7 = I 2 I 1 I 0 En

8 Decoder Application: universal set {Decoder, OR} Example: Implement functions f 1 (a,b,c) =  m(1,2,4) f 2 (a,b,c) =  m(2,3), andf 3 (a,b,c) =  m(0,5,6) with a 3-input decoder and OR gates. I0I0 y0y1..y7y0y1..y7 c b a I1I1 I2I2 0123456701234567 En y1y1 y2y2 y4y4 f1f1 y2y2 y3y3 f2f2 y0y0 y6y6 f3f3 y5y5

9 OR minterms Decoders

10 Tree of Decoders Implement a 4-2 4 decoder with 3-2 3 decoders. I0I0 y0y1y7y0y1y7 I1I1 I2I2 0123456701234567 I0I0 y 8 y 9 y 15 I1I1 I2I2 0123456701234567 a d c b

11 Implement a 6-2 6 decoder with 3-2 3 decoders. En D0D0 I 2, I 1, I 0 D1D1 y0y0 y7y7 y8y8 y 15 D7D7 y 56 y 63 En I 2, I 1, I 0 I 5, I 4, I 3 Tree of Decoders … …

12 2. Encoder Definition Logic Diagram Priority Encoder

13 2. Encoder: Definition y n-1 … y 0 En A I 2 n -1 … I 0 8 inputs 3 outputs y0y0 y1y1 y2y2 0123456701234567 En At most one I i = 1. (y n-1,.., y 0 ) = i if I i = 1 &  n = 1 (y n-1,.., y 0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. I i = 1 A = 0 otherwise. Encoder Description: A I0I0 I7I7 012012

14 Encoder: Logic Diagram En I1I1 I3I3 I5I5 I7I7 y0y0 I2I2 I3I3 I6I6 I7I7 y1y1

15 En I4I5I6I7I4I5I6I7 y2y2 I0I0 I1I1 I6I6 I7I7 A.. Encoder: Logic Diagram

16 Priority Encoder: Definition Description: Input (I 2 n -1,…, I 0 ), Output (y n-1,…,, y 0 ) (y n-1,…,, y 0 ) = i if I i = 1 & En = 1 & I k = 0 for all k > i (high bit priority) or for all k< i (low bit priority). E o = 1 if En = 1 & I i = 0 for all i, G s = 1 if En = 1 & i s.t. I i = 1. E (G s is like A, and E o tells us if enable is true or not). 0123456701234567 En EoGs I0I0 I7I7 y0y0 y1y1 y2y2 012012

17 Priority Encoder: Implement a 32-input priority encoder w/ 8 input priority encoders (high bit priority). y 32, y 31, y 30 I 31-24 Eo Gs y 22, y 21, y 20 I 25-16 Eo Gs y 12, y 11, y 10 I 15-8 Eo Gs y 02, y 01, y 00 I 7-0 Eo Gs En

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