1. Strong Error Detection for Control Units Against Advanced Attackers Kahraman Daglar Akdemir Advisor: Berk Sunar Electrical and Computer Engineering MOTIVATION Current computational resources can rarely challenge the existing cryptographic algorithms implemented on security devices such as smart cards. Key sizes that are used in these devices are secure against brute-force attacks. The real danger is the so called “side-channel” attacks, in which the attacker can reach to secret information (e.g. secret key) using implementation specific side-channels. PROPOSED SOLUTION Error Detection Mechanism Publications 2 Active Attacks Optical Fault Injection EM-Induced Fault Injection Power and Clock Fault Injection Passive Attacks Power Analysis Timing Analysis Electro-Magnetic Analysis Classes of Side-Channel Attacks Example optical fault injection attacks [1-2] High density optical lasers cause bit flips on specific parts of an IC and this can reveal information about the secret key. There are many publications suggesting solutions to fault injection attacks, such as concurrent error detection (CED). However, these solutions focus on the datapath parts of the cryptographic hardware and the control units (e.g. Finite State Machines) are left totally vulnerable to active side-channel attacks. Gaubatz et al. [3] observed this gap existing on the control unit security and proposed a linear protection scheme where he decodes state and output variable using a linear error detection code. However, this solution is far from being a “robust” one. An example fault attack on a FSM implementing Montgomery Ladder Algorithm [3] Karpovsky and Taubin [4] proposed a new class of non-linear codes which can provide a robust error detection solution against fault attacks. We suggest that given the input, state and output assignments, we can write the next-state and output as an algebraic function using Lagrange interpolation. In this case, if we apply a similar non-linear error detection code to the input, output, and state encodings, we will have a measurably robust error detection scheme for the control unit. Case Study for the FSM diagram shown above Arithmetic hardware implementation of the next-state logic for the example case study Efficient MUX based hardware implementation of the next-state logic for the example case study RESULTS Area Overhead and Scaling Robustness To be able to add error detection capabilities to the proposed schemes, we need redundancy. We define the following error check function on a variable to obtain a non-linear error check-sum. Consequently, states and inputs will now be decoded as (s,h(s)) and (i,h(i)). Basically, there are two paths that are non- linear to each other. The check-sum of the expected output is generated using the predictor and the check-sums of the inputs. If the expected check-sum does not match with the actual check-sum, then this means that an error is injected. So the secret information is reseted. The error detection probabilities for both the arithmetic and MUX based efficient implementations are indicated. As can be observed (top), for all possible error vectors that can be injected, the minimum error detection probability is ~0.985 for the arithmetic case. Another important point is that this probability is distributed uniformly. The error detection probability behaviour is more spiky in the efficient MUX based scheme due to the non-uniform distribution at the outputs of the MUXs (bottom). The minimum error detection probability is ~0.968 for this case. The implementation results related to the example in the case study are summarized in the above table. The area overhead associated with the efficient MUX based implementation is on the order of %197 (See the above table). This provides better performance than the linear method solution proposed by Gaubatz [3]. Plus, the minimum error detection probability is maximized in our case. When we look how the proposed methods scale for different FSMs, we observe that the arithmetic case shows a cubic behaviour (top) while the efficient MUX based case is quadratic (bottom) with respect to the number of states in the FSM. K. D. Akdemir, B. Sunar. Strong Error Detection for Control Units Against Advanced Attackers. IEEE Transactions on Computers (Submitted for Review). References [1] Schmidt, J.M. and Hutter M. "Optical and EM Fault-Attacks on CRT-based RSA: Concrete Results", Austrochip 2007 - Proceedings of the 15th Austrian Workshop on Microelectronics, ISBN 978-3-902465-87-0, Oct 2007. [2] Skorobogatov, S. P. and Anderson, R. J. 2003. Optical Fault Induction Attacks. In Revised Papers From the 4th international Workshop on Cryptographic Hardware and Embedded Systems (August 13 - 15, 2002). B. S. Kaliski, Ç. K. Koç, and C. Paar, Eds. Lecture Notes In Computer Science, vol. 2523. Springer-Verlag, London, 2-12. [3] Sunar, B., Gaubatz, G., and Savas, E. 2008. Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults. IEEE Trans. Comput. 57, 1 (Jan. 2008), 126-138. [4] Mark Karpovsky and Alexander Taubin. A new class of nonlinear systematic error detecting codes. IEEE Trans Info Theory, 50(8):1818–1820, 2004.