1. Department of Electrical and Computer Engineering M.A. Basith, T. Ahmad, A. Rossi *, M. Ciesielski ECE Dept. Univ. Massachusetts, Amherst * Univ. Bretagne Sud, Lorient France ALGEBRAIC APPROACH TO ARITHMETIC DESIGN VERIFICATION

2. 2 Department of Electrical and Computer Engineering Introduction  Design Verification A dominating factor in design flow  Formal Verification Equivalence checking, model checking, property checking, etc. Verification of combinational designs – a solved problem Remains challenging for sequential circuits, but big progress  Verification of Arithmetic Designs and Data-paths Difficult, bit blasting makes it not scalable  This Work Verifying functionality of arithmetic designs Not exactly EC, but comparing design to a “golden model” (reference signature) Using algebraic rather than Boolean or symbolic approach

3. 3 Department of Electrical and Computer Engineering Related Work 4 1 0 x0 x1 x2 1 2 4 y0 y1 y2 2 1  Canonical representations BDD, too fine-grained [Bryant’85] BMD [Bryant’95] and TED [Ciesielski’06], t oo-low grained cannot express output bits as a function of word-level inputs  ILP based Data-path Verification [Brinkmann’02] Transforms bit-vector expressions into ILP constraints Cannot handle large designs, variable width limitation  Term rewriting for RTL equivalence checking [Vasudevan’07] Database of rewrite rules for typical multiplier implementation schemes Cannot be automated for non-standard implementations  Symbolic Algebra Methods [Shekhar’05] Solving vanishing polynomial (modulo 2 m ) using finite ring algebra Uses Grobner basis, scripting with Maple tools Cannot handle complex arithmetic designs

4. 4 Department of Electrical and Computer Engineering Related Work, cont’d.  Arithmetic Bit-Level (ABL) [Wienand CAV’08, Pavlenko DATE’11] Represents design as network of HA (ABL) Creates algebraic expression of Boolean-level information Requires structural similarity Complex math, Grobner basis Can it handle very large designs ?  ABL provided main motivation for our approach No need for Grobner basis No need for deriving and manipulating large polynomials Use only linear expressions

5. 5 Department of Electrical and Computer Engineering Our Approach  Represent arithmetic design on ABL Network of gates, HAs and FAs  Write linear equations to represent data flow  Compute algebraic signature of the network  Prove functionality by matching signature with reference signature (specification)

6. 6 Department of Electrical and Computer Engineering Arithmetic Network Model  Half-Adder Binary inputs ( a, b) Binary outputs ( S, C)  Full-Adder Binary inputs ( a, b, c in ) Binary outputs ( S, C)

7. 7 Department of Electrical and Computer Engineering Gate Level Models x + y = 1

8. 8 Department of Electrical and Computer Engineering Mathematical Representation x I - Inputs x O - Outputs x S - Internal signals Network Equations:

9. 9 Department of Electrical and Computer Engineering Mathematical Representation x I - Inputs x O - Outputs x S - Internal signals Network Equations: In matrix form: A x = b A – m x n constraint matrix (network) x – n-vector representing signals b – constant vector A x b

10. 10 Department of Electrical and Computer Engineering Reference Signature Functionality provided by user Sig I (N) = x 1 + x 2 + x 3 + x 4 + x 5 + x 6 + x 7 (input signature) Sig O (N) = 4x 8 + 2x 9 + x 10 (output signature) Reference Signature Ref(N) = Sig O (N) – Sig I (N) = 4x 8 + 2x 9 + x 10 - x 1 - x 2 - x 3 - x 4 - x 5 - x 6 - x 7

11. 11 Department of Electrical and Computer Engineering Reference Signature - definition  Reference Signature, Ref(N) Provides relationship between input and output variables Difference between the output signature and input signature Ref(N) = Sig O − Sig I Mathematically r O – output signature vector x O – primary output vector r I – input signature vector x I – primary input vector

12. 12 Department of Electrical and Computer Engineering Reference Signature - example Reference Signature for a 7-3 counter: or, equivalently Output Signature = 3-bit encoding of the output word Input Signature = sum of the input bits T

13. 13 Department of Electrical and Computer Engineering Algebraic Signature The network is similarly represented by its Algebraic Signature  Algebraic signature, Sig(N) Defines relationship between input, output and internal signal variables (x I x O x S ) It is a linear combination of x = [x I x O x S ] T where r T = [r I r O r S ]  It can be computed directly from matrix A A T α = r by choosing a linear combination α of rows of matrix A  Goal: compute α that will eliminate internal variables x S (r S = 0) the resulting signature should match the reference signature

14. 14 Department of Electrical and Computer Engineering Verification Goal  Prove that the network (implementation) matches the specification given by the reference signature. That is:  Given the reference signature Ref(N) (specification)  Compute algebraic signature Sig(N) (implementation)  Check if Sig(N) = Ref(N) ?  For the network to be correct the two signatures should match

15. 15 Department of Electrical and Computer Engineering Computing Algebraic Signature n – total number of signals in the network m – number of linear equations in the system A x = b A I x I + A O x O + A S x S = b A I – columns associated with x I x I - primary input variables A O – columns associated with x O x O - primary output variables A S - columns associated with x S x S - internal signal variables

16. 16 Department of Electrical and Computer Engineering Computing Algebraic Signature  Algebraic signature Sig(N) relates I/O and internal signals  Sig(N) can be obtained as a linear combination of rows of A that matches Ref(N) α – vector of integer coefficients that reduces matrix A to signature vector r  Ideally, want r s = 0 (eliminate all internal signals) 0 (ideally)

17. 17 Department of Electrical and Computer Engineering Completing the Signature  If the system is infeasible, relax r S and solve for α If there is no solution: design is incorrect  Otherwise compute r S If r S = 0, design is correct  What oif r S ≠ 0, is the design incorrect?

18. 18 Department of Electrical and Computer Engineering Computing Algebraic Signature – example (r s =0) x I = {x 1, x 2, x 3,x 4, x 5,x 6, x 7 } x O = {x 8, x 9, x 10 } x S = {x 11, x 12, x 13, x 14, x 15 } Aα r * -x 1 –x 2 –x 3 +2x 11 +x 12 -x 4 –x 5 –x 6 +2x 13 +x 14 -x 7 +x 10 –x 12 –x 14 +2x 15 4x 8 +2x 9 -2x 11 -2x 13 -2x 15 -x 1 –x 2 –x 3 –x 4 –x 5 –x 6 –x 7 +4x 8 +2x 9 +x 10 = α r Aα r

19. 19 Department of Electrical and Computer Engineering Computing Algebraic Signature – example (r s  0) Ref(N ) Sig(N) Network equations: Residual Expression r S set to 0, system is infeasible r S relaxed, gives residual expression

20. 20 Department of Electrical and Computer Engineering Residual Expression  Residual Expression, RE(N) = Sig(N) − Ref(N) = r S T x S An expression associated with the internal signals x S  RE(N) should evaluate to zero for the design to be correct Need additional Boolean constraints  To prove RE = 0, we need additional constraints to impose on N Structural Constraints Caused by fanout of internal signals, equality constraints Boolean Constraints Internal signals of FA, can be propagated in the network

21. 21 Department of Electrical and Computer Engineering Proving RE = 0 with Boolean constraints Reference Signature: Computation of Signature: Algebraic Signature: Residual Expression: Boolean Constraints:  RE(N) = 0 Now Ref(N) = Sig(N): design is correct

22. 22 Department of Electrical and Computer Engineering Functional Verification Flow

23. 23 Department of Electrical and Computer Engineering Comparison with SMT Solvers Without Boolean constraints, RE ≠ Φ. (MO = out of memory 4GB, TO = timeout after 1800 sec) With Boolean constraints, RE = Φ.  Problem can be modeled as SAT  Need to show that is unSAT

24. 24 Department of Electrical and Computer Engineering Results – Large Multipliers CPU runtime for computing algebraic signature for n-bit integer multipliers with additional constraints propagated in the network.

25. 25 Department of Electrical and Computer Engineering Results – Booth-encoded Multipliers CPU runtime for computing algebraic signature for n-bit integer Booth-encoded multipliers with additional constraints propagated in the network. Complexity: O(N 2 ) in number of gates

26. 26 Department of Electrical and Computer Engineering Conclusions  Developed a new technique for functional verification of arithmetic circuits based on computing algebraic signature  Application RTL and gate-level Verification Given reference signature, system tries to match the signatures Equivalence Checking Comparing two networks on the basis of their signatures Property Checking Represent property P by its algebraic signature, Sig P (N) = r T x P Check for consistency with reference signature A P T α = r P Extracting circuit behavior Use Sig O (N) to compute Sig I (N)  Limitations: limited to linear networks (Wallace trees, etc.)

27. 27 Department of Electrical and Computer Engineering Thank You

28. 28 Department of Electrical and Computer Engineering Outline  Introduction and Motivation  Related Work  Algebraic Modeling of Arithmetic Networks  Mathematical Formulation Computing the signature Residual expression and Boolean constraints  Relation to SMT Techniques  Results  Conclusion and Future Work

29. 29 Department of Electrical and Computer Engineering Verification Methods  Boolean methods Good for gate-level designs Inefficient for arithmetic designs  Decision diagrams and SAT solvers Requires “bit-blasting” (too low-level for arithmetic)  Symbolic Algebra Too high level: limited to polynomial expressions or infinite precision  SMT Generalization of Boolean SAT Lack of adequate models to handle arithmetic designs  This Work Functional verification of arithmetic circuits by computing algebraic signature

30. 30 Department of Electrical and Computer Engineering Related Work - Summary  Decision diagrams and Boolean SAT Not able to handle arithmetic functions efficiently  ILP Methods Computationally prohibitive for large designs  Symbolic Algebra Limited to small designs that can be represented as polynomials  ABL Methods Assumes structural similarity, which is often absent Uses Grobner basis (overkill ?)  Our Method No assumption about structural similarity Handles arithmetic on bit-level using algebra Fast and scalable (but limited to linear networks)

31. 31 Department of Electrical and Computer Engineering Complexity Graph Computational complexity of our approach Complexity:O(N 2 )

32. 32 Department of Electrical and Computer Engineering Future Work  Need to learn additional Boolean Constraints Is this problem as difficult as the original one?  Data-Path Verification Obtain a reference signature for the entire data-path Partition design into smaller blocks  Debugging Identify bugs in the circuit Analyze Simplex phase I (pre-solver) of the LP solver If LP is infeasible, non-zero values of variables provide information which equations prevent the LP from being feasible If LP is feasible, but RE cannot be reduced to zero, content of RE will be used to reason about bugs