1. Software-defined Radio using Xilinx (SoRaX) By: Anton Rodriguez & Mike Mensinger Advised by: Dr. In Soo Ahn & Dr. Yufeng Lu

2. Outline  Brief project overview/introduction  Project Goals  Prior work and supplements  Background  Dissection of Flowchart  Requirements  Equipment  Schedule

3. Project Overview  A Software-defined Radio (SDR) offers a flexible solution for many of today’s communication needs.  The objective of this project is to design a communication radio system on the FPGA board.  The main focus will lie on the carrier synchronization and phase ambiguity correction from the received data.  We will start by designing a Simulink model of the entire system and then implement it on the SignalWave Virtex II FPGA board.

4. Project Goals  Gain an in-depth understanding about the FPGA implementation of carrier synchronization.  Construct a working Simulink model.  Implement the Simulink model on the FPGA board.  Regenerate the carrier and symbol timing to decode the transmitted digital data.  Achieve fast acquisition of carrier synchronization and symbol timing through efficient Xilinx programming.  Create a test signal of known hard-coded values (preamble) to estimate the channel state.  If time permits, implement different modulation schemes (i.e. 16-QAM).

5. Previous Work / Supplements  Xilinx 11.1 Example – sysgen Costas Loop Referenced Phase-Locked Loop (PLL) FilterReferenced Phase-Locked Loop (PLL) Filter  FPGA Implementation of Carrier Synchronization for QAM Receivers By Chris Dick (Xilinx, Inc.)By Chris Dick (Xilinx, Inc.)  Previous Senior Project on QPSK receiver With phase-locked loopWith phase-locked loop Incomplete…Incomplete…

6. Background  E E 332 QPSK Project  Wireless communication introduces distortions due to multi-paths  Need to regenerate the in-phase carrier signal

7. High Level Flowchart Phase-Locked Loop

8. Corrected Signal + -

9. Loop Filter

10. Requirements  The model shall operate with a system clock of 50 MHz.  There shall be an explicit sampling period of 1/8 throughout the Simulink model.  The sampling frequency for the model should be 12.5 MHz.  We shall use the DDS compiler 2.0 to simulate our Voltage Controlled Oscillator (VCO) for the Phase-Locked Loop.  The frequency offset provided should be no larger than 1 kHz.  We shall follow the FCC Regulations for Radio Frequency Devices Stay outside of the restricted bands of operationStay outside of the restricted bands of operation

11. Equipment  SignalWave Virtex II FPGA  Xilinx - ISE 9.2 Compiler  Virtex 4 FPGA

12. Progress  To this point, we have dissected all of the models we were given.  Researched phase-locked loops and their components.  Isolated components have been tested to be functional: Phase detectorPhase detector Loop filterLoop filter DDS compilerDDS compiler  Dr. Lu’s revision

13. Schedule WeeksTasks (Winter Break) Compile a functional Simulink model Design Loop Filter 1 - 2 Load model onto the Virtex 4 2 - 5 Develop training sequence 5 - 9 Develop an algorithm to correct phase ambiguity of QPSK symbols 10 - 13 Implement 16 – QAM modulation scheme 13 – 15 Prepare Final Report and Oral Presentation

14. Questions?