1. Technical University of Lodz Department of Microelectronics and Computer Science Elements of high performance microprocessor architecture Shared-memory systems Shared-memory architecture CPUmemory peripheralCPUperipheral CPU Bus architecture Less expensive, but allowing only for one transfer at the time CPU peripheral memory CPU Crossbar architecture Costly, but allowing several transfers take place simultaneously 3All processors share the same view of the memory, each CPU can access any part of memory and peripherals 3Necessity of specialised hardware arbitration for memory access and multiprocessing/multithreading operating system

2. Technical University of Lodz Department of Microelectronics and Computer Science Elements of high performance microprocessor architecture Shared-memory systems Effect of Cache 3Reduction of traffic - lower demand on system bus bandwidth 3Memory access by one processor does not keep others waiting CPU Main memory CPU Cache XX XX X 7Cache Coherency problem: - who has the ‘true’ value of variable ? - how to let others know about the changes ?

3. Technical University of Lodz Department of Microelectronics and Computer Science Elements of high performance microprocessor architecture Cache coherency protocol Shared-memory systems 3Write-invalidate policy Snooping - monitoring the bus activity, independently from the processor CPU Main memory Cache tag + data Snoop tag CPU Cache tag + data Snoop tag Writing to cache causes all other copies to be invalidated, preferred with write-back caches due to reduced bus traffic 3Write-update policy Data written to cache is broadcast to all other caches for update

4. Technical University of Lodz Department of Microelectronics and Computer Science Elements of high performance microprocessor architecture Shared-memory systems Cache coherency protocol Coherency requirement adds new information (status) to each cache line Read-Only (Clean) - line is not written and may be shared Read/Write (Dirty) - line is written and may not be shared Invalid - line contains no valid data Cache line state transitions cause by bus snooping Clean Invalid Dirty Read or write miss by another processor Write miss by another processor or invalidate signal on bus Other cache-state models: MESI: Modified, Exclusive, Shared, Invalid Clean Invalid Dirty Read missWrite miss Write (hit or miss) Read miss Write hit Cache line state transitions cause by processor (Write line back)