1. cpsc614 Lec 1.1 Based on Lectures by: Prof. David E Culler Prof. David Patterson UC Berkeley CPSC 614:Graduate Computer Architecture 2006 Spring Introduction

2. cpsc614 Lec 1.2 Outline Why Take CPSC 614? Fundamental Abstractions & Concepts Instruction Set Architecture & Organization Pipelined Instruction Processing Performance The Memory Abstraction Summary

3. cpsc614 Lec 1.3 What is “Computer Architecture”? I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation Datapath & Control Layout

4. cpsc614 Lec 1.4 Why take CPSC 614? To design the next great instruction set?...well... Tremendous organizational innovation relative to established ISA abstractions Many New instruction sets or equivalent –embedded space, controllers, specialized devices,... Design, analysis, implementation concepts vital to all aspects of EE & CS –systems, PL, theory, circuit design, VLSI, comm. Equip you with an intellectual toolbox for dealing with a host of systems design challenges

5. cpsc614 Lec 1.5 Coping with CPSC 614 Students with too varied background? Review: CPSC 321 and/or “Computer Organization and Design (COD)2/e” –Chapters 1 to 8 of COD if never took prerequisite –If took a class, be sure COD Chapters 2, 6, 7 are familiar FAST review this week of basic concepts

6. cpsc614 Lec 1.6 Review of Fundamental Concepts Instruction Set Architecture Machine Organization Instruction Execution Cycle Pipelining Memory Bus (Peripheral Hierarchy) Performance Iron Triangle

7. cpsc614 Lec 1.7 Example Hot Developments ca. 2006 Manipulating the instruction set abstraction –itanium: translate ISA64 -> micro-op sequences –transmeta: continuous dynamic translation of IA32 –tinsilica: synthesize the ISA from the application –reconfigurable HW Virtualization –vmware: emulate full virtual machine –JIT: compile to abstract virtual machine, dynamically compile to host Parallelism –wide issue, dynamic instruction scheduling, EPIC –multithreading (SMT) –chip multiprocessors Communication –network processors, network interfaces Exotic explorations –nanotechnology, quantum computing High performance + Energy Efficiency + Reliability !!

8. cpsc614 Lec 1.8 Forces on Computer Architecture Computer Architecture Technology Programming Languages Operating Systems History Applications (A = F / M)

9. cpsc614 Lec 1.9 Amazing Underlying Technology Change

10. cpsc614 Lec 1.10 A take on Moore’s Law

11. cpsc614 Lec 1.11 Technology Trends Clock Rate: ~30% per year Transistor Density: ~35% Chip Area: ~15% Transistors per chip: ~55% Total Performance Capability: ~100% by the time you graduate... –3x clock rate (3-4 GHz) –10x transistor count (1 Billion transistors) –30x raw capability plus 16x dram density, 32x disk density

12. cpsc614 Lec 1.12 Performance Trends

13. cpsc614 Lec 1.13 Measurement and Evaluation Architecture is an iterative process -- searching the space of possible designs -- at all levels of computer systems Good Ideas Mediocre Ideas Bad Ideas Cost / Performance Analysis Design Analysis Creativity

14. cpsc614 Lec 1.14 The Instruction Set: a Critical Interface instruction set software hardware

15. cpsc614 Lec 1.15 Levels of Representation High Level Language Program Assembly Language Program Machine Language Program Control Signal Specification Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw$15,0($2) lw$16,4($2) sw$16,0($2) sw$15,4($2) 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 °°°° ALUOP[0:3] <= InstReg[9:11] & MASK

16. cpsc614 Lec 1.16 Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions

17. cpsc614 Lec 1.17 Organization Logic Designer's View ISA Level FUs & Interconnect Capabilities & Performance Characteristics of Principal Functional Units –(e.g., Registers, ALU, Shifters, Logic Units,...) Ways in which these components are interconnected Information flows between components Logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level (RTL) Description

18. cpsc614 Lec 1.18 Review: MIPS R3000 (core) 0 r0 r1 ° r31 PC lo hi Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC Data types ? Format ? Addressing Modes? Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JAL, JR, JALR BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL 32-bit instructions on word boundary

19. cpsc614 Lec 1.19 Types of Internal Storage Stack, Accumulator, A Set of Registers

20. cpsc614 Lec 1.20 Review: Basic ISA Classes Accumulator: 1 addressadd Aacc  acc + mem[A] 1+x addressaddx Aacc  acc + mem[A + x] Stack: 0 addressaddtos  tos + next General Purpose Register: 2 addressadd A BEA(A)  EA(A) + EA(B) 3 addressadd A B CEA(A)  EA(B) + EA(C) Load/Store: load Ra RbRa  mem[Rb] store Ra Rbmem[Rb]  Ra

21. cpsc614 Lec 1.21 Instruction Formats Variable: Fixed: Hybrid: … Addressing modes –each operand requires addess specifier => variable format code size => variable length instructions performance => fixed length instructions –simple decoding, predictable operations With load/store instruction arch, only one memory address and few addressing modes => simple format, address mode given by opcode

22. cpsc614 Lec 1.22 MIPS Addressing Modes & Formats Simple addressing modes All instructions 32 bits wide oprsrtrd immed register Register (direct) oprsrt register Base+index + Memory immedoprsrt Immediate immedoprsrt PC PC-relative + Memory

23. cpsc614 Lec 1.23 Cray-1: the original RISC Op 015 RdRs1R2 26 89 Load, Store and Branch 35 Op 015 RdRs1Immediate 26 8935150 Register-Register

24. cpsc614 Lec 1.24 VAX-11: the canonical CISC Rich set of orthogonal address modes –immediate, offset, indexed, autoinc/dec, indirect, indirect+offset –applied to any operand Simple and complex instructions –synchronization instructions –data structure operations (queues) –polynomial evaluation Variable format, 2 and 3 address instruction

25. cpsc614 Lec 1.25 RISC vs. CISC Pipelining Ease of Hardware Implementation Simple Instructions Simple Addressing Mode Fixed-Length Formats Large Number of Registers MIPS, … Simple Compilers Powerful Addressing Mode Powerful Instructions Efficient Instruction Encoding Few Registers VAX

26. cpsc614 Lec 1.26 Review: Load/Store Architectures MEM reg ° no memory reference per ALU instruction - 3 address GPR ° Register to register arithmetic ° Load and store with simple addressing modes (reg + immediate) ° Simple conditionals compare ops + branch z compare&branch condition code + branch on condition ° Simple fixed-format encoding op rrr rrimmed offset

27. cpsc614 Lec 1.27 MIPS R3000 Instruction Set Architecture ° Machine Environment Target ° Instruction Categories  Load/Store  Computational  Jump and Branch  Floating Point (coprocessor) OP Rs Rt Rdsafunct OP Rs Rt Immediate OP jump target 3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO Registers I: R: J:

28. cpsc614 Lec 1.28 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

29. cpsc614 Lec 1.29 What’s a Clock Cycle? Old days: 10 levels of gates Today: determined by numerous time-of- flight issues + gate delays –clock propagation, wire lengths, drivers Latch or register combinational logic

30. cpsc614 Lec 1.30 Fast, Pipelined Instruction Interpretation Instruction Register Operand Registers Instruction Address Result Registers Next Instruction Instruction Fetch Decode & Operand Fetch Execute Store Results NI IF D E W NI IF D E W NI IF D E W NI IF D E W NI IF D E W Time Registers or Mem

31. cpsc614 Lec 1.31 Sequential Laundry Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? ABCD 304020304020304020304020 6 PM 789 10 11 Midnight TaskOrderTaskOrder Time

32. cpsc614 Lec 1.32 Pipelined Laundry Start work ASAP Pipelined laundry takes 3.5 hours for 4 loads ABCD 6 PM 789 10 11 Midnight TaskOrderTaskOrder Time 3040 20

33. cpsc614 Lec 1.33 Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “fill” pipeline and time to “drain” it reduces speedup ABCD 6 PM 789 TaskOrderTaskOrder Time 3040 20

34. Recap: A Single Cycle Datapath °Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit °We have everything except control signals (underline) Today’s lecture will show you how to generate the control signals 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel

35. cpsc614 Lec 1.35 5 Steps of MIPS Datapath Figure 3.1, Page 130, CA:AQA 2e Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc LMDLMD ALU MUX Memory Reg File MUX Data Memory MUX Sign Extend 4 Adder Zero? Next SEQ PC Address Next PC WB Data Inst RD RS1 RS2 Imm

36. cpsc614 Lec 1.36 5 Steps of MIPS Datapath Figure 3.4, Page 134, CA:AQA 2e Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc ALU Memory Reg File MUX Data Memory MUX Sign Extend Zero? IF/ID ID/EX MEM/WB EX/MEM 4 Adder Next SEQ PC RD WB Data Next PC Address RS1 RS2 Imm MUX

37. cpsc614 Lec 1.37 Visualizing Pipelining Figure 3.3, Page 133, CA:AQA 2e I n s t r. O r d e r Time (clock cycles) Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg Cycle 1Cycle 2Cycle 3Cycle 4Cycle 6Cycle 7Cycle 5

38. cpsc614 Lec 1.38 Its Not That Easy for Computers Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle –Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) –Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) –Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).

39. cpsc614 Lec 1.39 Review of Performance

40. cpsc614 Lec 1.40 Which is faster? Time to run the task (ExTime) –Execution time, response time, latency Tasks per day, hour, week, sec, ns … (Performance) –Throughput, bandwidth Plane Boeing 747 BAD/Sud Concorde Speed 610 mph 1350 mph DC to Paris 6.5 hours 3 hours Passengers 470 132 Throughput (pmph) 286,700 178,200

41. cpsc614 Lec 1.41 Performance(X) Execution_time(Y) n == Performance(Y) Execution_time(X) Definitions Performance is in units of things per sec –bigger is better If we are primarily concerned with response time –performance(x) = 1 execution_time(x) " X is n times faster than Y" means

42. cpsc614 Lec 1.42 Computer Performance CPU time= Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle CPU time= Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle Inst Count CPIClock Rate Program X Compiler X (X) Inst. Set. X X Organization X X Technology X inst count CPI Cycle time

43. cpsc614 Lec 1.43 Cycles Per Instruction (Throughput) “Instruction Frequency” CPI = (CPU Time * Clock Rate) / Instruction Count = Cycles / Instruction Count “Average Cycles per Instruction”

44. cpsc614 Lec 1.44 Example: Calculating CPI bottom up Typical Mix of instruction types in program Base Machine (Reg / Reg) OpFreqCyclesCPI(i)(% Time) ALU50%1.5(33%) Load20%2.4(27%) Store10%2.2(13%) Branch20%2.4(27%) 1.5

45. cpsc614 Lec 1.45 Example: Branch Stall Impact Assume CPI = 1.0 ignoring branches (ideal) Assume solution was stalling for 3 cycles If 30% branch, Stall 3 cycles on 30% OpFreqCyclesCPI(i)(% Time) Other 70%1.7(37%) Branch30%4 1.2(63%) => new CPI = 1.9 New machine is 1/1.9 = 0.52 times faster (i.e. slow!)

46. cpsc614 Lec 1.46 Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1:

47. cpsc614 Lec 1.47 Ex) Suppose we enhance a machine to make all floating-point instructions run five times faster. If the execution time of some benchmark before the floating-point enhancement is 20 seconds, what will speedup be if half of the 20 seconds is spent executing floating-point instructions?

48. cpsc614 Lec 1.48 Summary Modern Computer Architecture is about managing and optimizing across several levels of abstraction wrt dramatically changing technology and application load Key Abstractions –instruction set architecture –memory –bus Key concepts –HW/SW boundary –Compile Time / Run Time –Pipelining –Caching Performance Iron Triangle relates combined effects –Total Time = Inst. Count x CPI + Cycle Time

49. cpsc614 Lec 1.49 Instruction Pipelining Execute billions of instructions, so throughput is what matters –except when? What is desirable in instruction sets for pipelining? –Variable length instructions vs. all instructions same length? –Memory operands part of any operation vs. memory operands only in loads or stores? –Register operand many places in instruction format vs. registers located in same place?

50. cpsc614 Lec 1.50 MIPS R3000 ISA (Summary) Instruction Categories –Load/Store –Computational –Jump and Branch –Floating Point »coprocessor –Memory Management –Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target 3 Instruction Formats: all 32 bits wide Registers

51. cpsc614 Lec 1.51 Example: MIPS (Note register location) Op 312601516202125 Rs1Rd immediate Op 3126025 Op 312601516202125 Rs1Rs2 target RdOpx Register-Register 56 1011 Register-Immediate Op 312601516202125 Rs1Rs2/Opx immediate Branch Jump / Call