1. Analysis and Design of CMOS Analog Building Blocks
Márcio Cherem Schneider
Universidade Federal de Santa Catarina
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia
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2. Analysis and design of CMOS analog building blocks
Contents
The intrinsic gain stage
The source-coupled pair
The two-transistor current mirror
A self-biased current source
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Analysis and design of CMOS analog building blocks
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3. Analysis and design of CMOS analog building blocks
Summary of main design equations
Technology parameters
Forward and reverse currents
Size- and bias-related transistor parameters
UICM
0.35 um CMOS technology
Saturation voltage
Saturation
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

4. THE INTRINSIC GAIN STAGE - 1
VDD VI M1 + IB CL ID IL M2
Vmax
Vmin
maximum output swing
VDSsat1
VDSsat2
VDD vo vi
VTH
vo=vi Av
M1,M2 in saturation vi
VDD
Class A amplifier: SR->SR+. ~3 if
|AV0|dB
From UICM we find the dc voltage VTH at the input:
Low-frequency gain versus inversion level
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

5. Voltage gain vs frequency
THE INTRINSIC GAIN STAGE - 2
VDD VI M + IB CL ID IL
V-I converter (transconductor) followed by an I-V converter (output impedance)
|AV|dB  u b
-20 dB/dec
|AV0| CL go
gmvg vi + vg vo VO
Voltage gain vs frequency
is the transconductance
is the output impedance
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

6. Analysis and design of CMOS analog building blocks
THE INTRINSIC GAIN STAGE - 3
VDD VI M1 + IB CL ID IL CL go
gmvg vi + vg vo VO
ECF
Sizing and biasing: W, L, IB
Power-area tradeoff
How long can L be?
CIN and transit time are both proportional to L2 (for constant W/L)!
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

7. Noise current generator Input-referred noise model
THE INTRINSIC GAIN STAGE - 4 VO
VDD VI M1 + IB CL ID IL
MOST noise model
Thermal /f
Bias-dependent factor
Corner frequency
1/2 (WI)
2/3 (SI)
Noise current generator
Input-referred noise model
Noiseless MOST
- +
0.35 um CMOS technology
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

8. Analysis and design of CMOS analog building blocks
THE SOURCE-COUPLED PAIR -1
VSS IT +
vG1 - M1 M2 I1 I2
vG2
First order analysis:
Ideal current source
M1 & M2 in saturation  I1 & I2 independent of drain voltage;
Normalization 8 4 12 -4 -8
-12 1
it=1000
100 10
<1
I1/IT
I2/IT
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

9. Analysis and design of CMOS analog building blocks
THE SOURCE-COUPLED PAIR - 2
VSS IT +
vG1 - M1 M2 I1 I2
vG2
Offset voltage VOS = VG =VG2- VG1 such that
 ID= I2- I1=0
Simple model
ir =0 (sat)
The differential input voltage at the input required for  ID =0 is
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

10. Analysis and design of CMOS analog building blocks
THE SOURCE-COUPLED PAIR - 3
VSS IT +
vG1 - M1 M2 I1 I2
vG2
Uncorrelated  VT &  IS
Pelgrom’s model
(I) (II)
Notes:
0.35 um CMOS technology
(I) is dominant over (II) for
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11. THE TWO-TRANSISTOR CURRENT MIRROR - 1
VDD ii + vG - io vo M1 M2
1:1 iD vD
locus vD=vG vG vo
iD1
iD2
M1: iv converter
M2: vi converter
Basic principle VG1=VG2; VS1=VS2; vout>VDsat  ioii
Error due to difference in VD’s
Error due to mismatch
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

12. Analysis and design of CMOS analog building blocks
THE TWO-TRANSISTOR CURRENT MIRROR - 2 ii io M1 M2
VDD
ac analysis ii + v - io C1 C2
1:A
Noise analysis
Uncorrelated noise sources
iin io M1 M2 i1 i2
1:A
The effect of M1 on noise is A times greater than that of M2
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

13. Analysis and design of CMOS analog building blocks
CURRENT MIRROR: GAIN SCHEMES
Gain-of-two current mirrors
VDD II IO
1:2
W/L
Gain=A
Gain=1/(NM)
VDD ii
io==Aii
...... ii
io==ii/(NM)
...... . N M
VDD II IO
1/2:1
W/L
VDD ii
io==ii/A
......
Gain= 1/A
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

14. A SELF-BIASED CURRENT SOURCE – 1
SELF-CASCODE MOSFET (SCM)
Sat.
Triode
Applying UICM to both M1 & M2
The self-biased current source we have designed is based on the self-cascode MOSFET shown in the slide and the self-biased circuit shown in the previous slide. In our design, we have chosen N=1 through a unity-gain current mirror. VX is a PTAT voltage generated by means of a second self-cascode MOSFET biased in weak inversion. VX is copied to the source of M2 through a voltage following current mirror. The family of curves represents the variation of VX in terms of the inversion level of M2 for several values of . This factor accounts for the relative sizes of M1 and M2 and the current mirror gain. From the curves one can see that, for a given pair (, VX), the inversion level is poorly defined if M2 operates in weak inversion .In other words, the sensitivity of the inversion level to VX is extremely high in weak inversion. In our particular design example, we have chosen the nominal values of VX and  to be around 60 mV and 3.4 resulting in if2=3 and if1=10.2. The resulting gate-to-source voltage across M1 is around the threshold voltage plus 70 mV.
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Analysis and design of CMOS analog building blocks
Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia
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15. V-I CHARACTERISTICS OF THE SCM
A SELF-BIASED CURRENT SOURCE – 2
V-I CHARACTERISTICS OF THE SCM
Sat.
Triode
I2=NIx
In WI:
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

16. VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1
A SELF-BIASED CURRENT SOURCE – 3
VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1
When both M8 & M9 operate in WI:
1 B. Gilbert, AICSP vol. 38, pp , Feb. 2004
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

17. A self-biased current sourceVx
VFCM
A self-biased current source
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

18. Analysis and design of CMOS analog building blocks
Output current: Iref=10 nA
ISHn-channel100 nA, ISHp-channel40 nA
A SBCS – 5: DESIGN =1
Let us choose
M1 &M2 in MI: if2 = S2= S1, N = 1
=10 nA
VFCM
M3 &M4 in WI: if3(4) <<1
Let us choose if3=0.187 
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

19. Analysis and design of CMOS analog building blocks
A SBCS – 6: DESIGN
Summary
VFCM =1
=10 nA S if ir M1
0.01 10 M2 30 M3
1.13
0.187 M4
M8, M8(a) 1
0. 1
M9, M9(a)
MP (all)
2.5
0.1
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

20. A SBCS – 7 : IOUT vs. VDD AT CONSTANT T
NAMITEC Colloquium
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Analysis and design of CMOS analog building blocks
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Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia

21. Analysis and design of CMOS analog building blocks
NAMITEC Colloquium
Campinas
Analysis and design of CMOS analog building blocks
EMICRO II - Bahia
Analysis and Design of CMOS Analog Building Blocks EMICRO II - Bahia