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NAMITEC Colloquium Campinas - 2010 Analysis and design of CMOS analog building blocks1 Analysis and Design of CMOS Analog Building Blocks Márcio Cherem.

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Presentation on theme: "NAMITEC Colloquium Campinas - 2010 Analysis and design of CMOS analog building blocks1 Analysis and Design of CMOS Analog Building Blocks Márcio Cherem."— Presentation transcript:

1 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks1 Analysis and Design of CMOS Analog Building Blocks Márcio Cherem Schneider Universidade Federal de Santa Catarina

2 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks2 Contents 1. The intrinsic gain stage 2. The source-coupled pair 3. The two-transistor current mirror 4.A self-biased current source

3 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks3 Summary of main design equations Saturation Technology parameters Size- and bias-related transistor parameters 0.35 um CMOS technology UICM Saturation voltage Forward and reverse currents

4 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks From UICM we find the dc voltage V TH at the input: 4 THE INTRINSIC GAIN STAGE - 1 M 1,M 2 in saturation Class A amplifier: SR - >SR +. V max V min maximum output swing V DSsat1 V DSsat2 V DD vovo vivi V TH v o =v i AvAv vivi V DD 0 VIVI M1M1 + IBIB CLCL IDID ILIL M2M2 ~3 ifif 0 |A V0 | dB Low-frequency gain versus inversion level

5 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks5 VOVO V DD VIVI M + IBIB CLCL IDID ILIL CLCL gogo gmvggmvg vivi + vgvg vovo V-I converter (transconductor) followed by an I-V converter (output impedance) is the transconductance is the output impedance |A V | dB u b dB/dec |A V0 | Voltage gain vs frequency THE INTRINSIC GAIN STAGE - 2

6 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks6 VOVO V DD VIVI M1M1 + IBIB CLCL IDID ILIL CLCL gogo gmvggmvg vivi + vgvg vovo Power-area tradeoff How long can L be? Sizing and biasing: W, L, I B ECF C IN and transit time are both proportional to L 2 (for constant W/L)! THE INTRINSIC GAIN STAGE - 3

7 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks7 VOVO V DD VIVI M1M1 + IBIB CLCL IDID ILIL Bias-dependent factor Thermal 1/f MOST noise model Corner frequency 1/2 (WI)2/3 (SI) 0.35 um CMOS technology Noise current generator Input-referred noise model Noiseless MOST - + THE INTRINSIC GAIN STAGE - 4

8 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks8 V SS ITIT + v G1 - M1M1 M2M2 I1I1 I2I2 + v G2 - First order analysis: Ideal current source M 1 & M 2 in saturation I 1 & I 2 independent of drain voltage; Normalization THE SOURCE-COUPLED PAIR i t = <1<1 I 1 /I T I 2 /I T

9 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks9 V SS ITIT + v G1 - M1M1 M2M2 I1I1 I2I2 + v G2 - Offset voltage V OS = V G =V G2 - V G1 such that I D = I 2 - I 1 =0 Simple model The differential input voltage at the input required for I D =0 is THE SOURCE-COUPLED PAIR - 2 i r =0 (sat)

10 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks10 V SS ITIT + v G1 - M1M1 M2M2 I1I1 I2I2 + v G2 - Pelgroms model Uncorrelated V T & I S Notes: 0.35 um CMOS technology THE SOURCE-COUPLED PAIR - 3 (I) (II) (I) is dominant over (II) for

11 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks11 THE TWO-TRANSISTOR CURRENT MIRROR - 1 V DDi +vG-+vG- ioio vovo +-+- M1M1 M2M2 1:1 M 1 : i v converter M2: v i converter Basic principle V G1 =V G2 ; V S1 =V S2 ; v out >V Dsat i o i i iDiD vDvD locus v D =v G vGvG vovo i D1 i D2 Error due to difference in V D s Error due to mismatch

12 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks12 1:A i +v-+v- ioio C1C1 C2C2 i ioio M1M1 M2M2 V DD i in ioio M1M1 M2M2 i1i1 i2i2 1:A Uncorrelated noise sources Noise analysis ac analysis The effect of M 1 on noise is A times greater than that of M 2 THE TWO-TRANSISTOR CURRENT MIRROR - 2

13 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks13 Gain-of-two current mirrors V DDI IOIO 1/2:1 W/L V DDI IOIO 1:2 W/L CURRENT MIRROR: GAIN SCHEMES V DDi i o= =Ai i V DDi i o= =i i /A Gain=A Gain= 1/A i i o= =i i /(NM) N M Gain=1/(NM)

14 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks14 A SELF-BIASED CURRENT SOURCE – 1 Applying UICM to both M1 & M2 Sat. Triode SELF-CASCODE MOSFET (SCM)

15 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks15 V-I CHARACTERISTICS OF THE SCM In WI: Sat. Triode I 2 =NI x A SELF-BIASED CURRENT SOURCE – 2

16 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks16 VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS) 1 1 B. Gilbert, AICSP vol. 38, pp , Feb When both M 8 & M 9 operate in WI: A SELF-BIASED CURRENT SOURCE – 3

17 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks17 A self-biased current source VxVx VFCM VxVx A SELF-BIASED CURRENT SOURCE – 4

18 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks18 VFCM A SBCS – 5: DESIGN M 1 &M 2 in MI: i f2 = 10 S 2 = S 1, N = 1 Let us choose M 3 &M 4 in WI: i f3(4) <<1 Output current: I ref =10 nA I SHn-channel 100 nA, I SHp-channel 40 nA =1 =10 nA Let us choose i f3 =0.187

19 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks19 A SBCS – 6: DESIGN Sifif irir M1M M2M M3M M4M M 8, M 8(a) M 9, M 9(a) M P (all) VFCM =1 =10 nA Summary

20 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks20 A SBCS – 7 : I OUT vs. V DD AT CONSTANT T

21 NAMITEC Colloquium Campinas Analysis and design of CMOS analog building blocks21


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