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© 2010 Eric Pop, UIUCECE 598EP: Hot Chips Revisit CMOS Power Dissipation Digital inverter: –Active (dynamic) power –Leakage power –Short-circuit power.

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Presentation on theme: "© 2010 Eric Pop, UIUCECE 598EP: Hot Chips Revisit CMOS Power Dissipation Digital inverter: –Active (dynamic) power –Leakage power –Short-circuit power."— Presentation transcript:

1 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Revisit CMOS Power Dissipation Digital inverter: –Active (dynamic) power –Leakage power –Short-circuit power (ignored) 1 Roy & Prasad (2000)

2 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Leakage vs. Active Power Trends 2 W. Haensch, IBM J. Res. Dev. 50, 339 (2006)

3 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Some Observations with Leakage This is the “usual” (BSIM, Spice) leakage model The thermal voltage V T = k B T/q This model was derived for 3-dimensional carrier motion, impinging on a small energy barrier (what about 1-D or 2-D transistors?) This model assumes some average “junction temperature” T but T itself is unsteady during digital operation! (what about hot phonons?!) 3

4 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips What About Energy? Energy is a better metric when worried about battery life So look at energy, not power minimization: Critical difference: leakage energy depends on circuit delay, t p 4 ?

5 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Effects of Lowering V DD Easy observation: lowering V DD lowers power and energy… the latter up to a point! How low V DD ? It is theoretically possible to operate circuits near V DD ~ 50 mV, deep into the subthreshold regime! So… why not do it? 5 B. Zhai, IEEE Trans. VLSI Sys. 13, 1239 (2005)

6 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Energy-Voltage Trade-Off Remember, delay: At high V DD  I ON = I D,sat At low V DD delay too high, so leakage energy goes up as well 6 B. Zhai, IEEE Trans. VLSI Sys. 13, 1239 (2005) Optimum V DD !

7 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Principles of Low-Power Design Use the lowest possible supply voltage (V DD ) Use the smallest geometry, highest frequency devices BUT operate them at the lowest possible frequency (f) Use parallelism and pipelining to lower required frequency of operation Manage power by disconnecting power source when system is idle (sleep states) Design systems to have lowest requirements of performance for the given user functionality 7 Roy & Prasad (2000)

8 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Leakage Model: Closer Look Strongly (exponentially!) temperature dependent! Typically people use ΔT = PR TH where –ΔT is an average “junction temperature” –P is a time-averaged power dissipation (active + leakage) How do we calculate R TH ? And when is it OK to use it? 8

9 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips 9 Device Thermal Resistance Data Silicon-on- Insulator FET Bulk FET Cu Via Phase-change Memory (PCM) Single-wall nanotube Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006). High thermal resistances: SWNT due to small thermal conductance (very small d ~ 2 nm) Others due to low thermal conductivity, decreasing dimensions, increased role of interfaces Power input also matters: SWNT ~ 0.01-0.1 mW Others ~ 0.1-1 mW

10 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips 10 Modeling Device Thermal Response Steady-state models –Lumped: Mautry (1990), Goodson-Su (1994-5), Pop (2004), Darwish (2005) –Finite-Element L W D t BOX t Si Bulk Si FETSOI FET Bulk FET

11 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips 11 Modeling Device Thermal Response Transient Models –Lumped: Tenbroek (1997), Rinaldi (2001), Lin (2004) –Introduce C TH usually with approximate Green’s functions; heated volume is a function of time (Joy, 1970) –Finite-Element Temperature evolution of a step-heated point source into silicon half-plane (Mautry 1990) Simplest (~ bulk Si FET) Instantaneous T rise Due to very sharp heating pulse t ‹‹ V 2/3 / More general Temperature evolution anywhere (r,t) due to arbitrary heating function P(0<t’<t) inside volume V (dV’  V) (Joy 1970)

12 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Approaches for Thermal Resistance Time scale: –Transient –Steady-State Geometric complexity: –Lumped element (shape factors) –Analytic –Finite element (Fourier law) 12 + Interconnect

13 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Shape Factors Heat flux: q = Sk(T 1 -T 0 ) Equivalent thermal resistance R TH = 1/Sk 13 Sunderland, ASHRAE (1964), many others

14 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Ex: Heat Loss from Via + Interconnect 14 Estimating heat loss (thermal resistance) “looking into” one Cu line: Typical values w Si z BOT 2r SiO 2 d Chen, 2000 z TOP Cu K/mW (bot – top) Chen, Li, Rosenbaum, Kang, IEEE TCAD ICS 19, 197 (2000)

15 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Many Shape Factors (Compact Models) 15

16 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Thermal-Electrical Cheat Sheet 16

17 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Obtaining the Temperature Distribution Now we want temperature distribution T(x) in 1-D Consider power in/out of a 1-D element Simplest case: Si layer on SiO 2 /Si substrate (SOI) Or interconnect on thermally insulating SiO 2 17

18 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips 1-D Interconnect with Heat Generation 18 Si t ox SiO 2 d T0T0 L W x x+dx Energy balance equation for 1-D element “dx”: pick units of J/cm 3 or W/cm 3 (W = J/s) Energy In (here, Joule heat) = Energy Out (left, right, bottom) + Change in Internal Energy Heat: Electrical:

19 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Ex: 1D Rectangular Nanowire 19

20 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips 1-Dimensional Heat Equation 20 SiO 2 k TT g TT unsteady (transient) steady, with convection

21 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Interconnect Heat Loss and Crosstalk 21

22 © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Carbon Nanotube (Cylinder) 22 TT Role of thermal contact resistance Role of cylindrical heat spreading (shape factor!) E. Pop et al. J. Appl. Phys. 101, 093710 (2007)

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