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7.10 e 7.11 Contadores com reset Contadores BCD, em anel e Johnson
Figure 7.26 A modulo-6 counter with synchronous reset Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock Count Q 0 Q 1 Q 2 (a) Circuit (b) Timing diagram
Figure 7.27 A modulo-6 counter with asynchronous reset T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count (b) Timing diagram
Figure 7.28 A two-digit BCD counter Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock Q 3 0 D 3 Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock Q 3 0 D 3 BCD 0 1 Clear
Figure 7.29 Ring counter
yoyo y1y1 y2y2 y3y3 wowo w1w1 EnEn QoQo Q1Q1 Clk Clear
Figure 7.30 Johnson counter D Q Q Clock D Q Q D Q Q Q 0 Q 1 Q n1– Reset
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