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Published byAshley Monroe
Modified over 5 years ago
7.10 e 7.11 Contadores com reset Contadores BCD, em anel e Johnson
Figure 7.26 A modulo-6 counter with synchronous reset1 Enable D Q D Q 1 1 D Q 2 2 Load Clock Clock (a) Circuit Clock Q Q 1 Q 2 Count 1 2 3 4 5 1 (b) Timing diagram Figure A modulo-6 counter with synchronous reset
Figure 7.27 A modulo-6 counter with asynchronous reset1 T Q T Q T Q Q Q Q 1 2 Clock Q Q Q (a) Circuit Clock Q Q 1 Q 2 Count 1 2 3 4 5 1 2 (b) Timing diagram Figure A modulo-6 counter with asynchronous reset
Figure 7.28 A two-digit BCD counter1 Enable D Q D Q 1 1 BCD D Q 2 2 D Q 3 3 Load Clock Clock Clear Enable D Q D Q 1 1 BCD D Q 1 2 2 D Q 3 3 Load Clock Figure A two-digit BCD counter
Figure Ring counter
yo y1 y2 y3 w1 wo En Q1 Qo Clk Clear
Figure 7.30 Johnson counterQ Q Q 1 n – 1 D Q D Q D Q Q Q Q Reset Clock Figure Johnson counter
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