1. EES: Burn – in test Eliminate infant mortality: Not possible to detect it with AOI, FPT, X-ray or ICT! 1

2. EES: Burn – in test Preliminary version already defined: * Previous experience from AUGER and ANTARES 2 A first cold cycle with 10 minutes dwell time at 0ºC 16 hours burn-in at 70 °C More or less 10 cycles with 5°C / minutes ( -0 to +70°C) fall and rise time and 10 minutes dwell time Maximum temperature : 70°C (or maximum specified components temperature) Minimum temperature : 0°C (or minimum specified components temperature) The board should be ON and a minimum functional test should be performed if possible (using caps and loops on input/output ports and serial bus like Ethernet or RS232… for communication with board inside oven) Make a 5 minutes Power Off during minimum and maximum dwell time of the penultimate cycle To be use as reference: the test can be adapted to the needs of each board

3. The following formula was proposed in a 2005 article by Mark G. Lawrence in the Bulletin of the American Meteorological Society: Tdew = T - ((100 - RH)/5) RH = 30 % -> Tdew= 14 º smaller than ambience temperature. Good enough? RH = 40 % -> Tdew = 12 º Burn-in Test: Dew Temperature Relative humidity 3

4. Production Strategy: CLBv2: Manufacturer: AOI + x-ray BGA components + functional tests (tender close) KM3NeT: Burn-in tests + second functional test (With the PB) ??? (possibility to outsource them – no PON money) PBv2: Manufacturer: ? KM3NeT: ? PMT BASES: Manufacturer: Tender specifications being finished: Probably AOI + System On Chip. KM3NeT: Functional test on the integration tests. EES not clear yet. Octopusv3: Manufacturer: ( AOI + functional test + EES + functional test) ? KM3NeT: Nothing ? (Ideal scenario!) Nanobeacon: Manufacturer: (AOI + functional test + EES + functional test) KM3NeT: Nothing? (ideal scenario!) 4

5. CLBv2 + PBv2 burn-in test: Together is simple to supply them (Only two cables) Power supply with enouth current needed or several used (To be Study) In test measurements using USB UART + USB driver expansor connected to one computer. Software needed -> Not now, in October Number of board per EES to be determined: 20 a good number 600 / 20 = 30 cycles 3 cycles per week -> 3 DU per week 5

6. PBv2 modifications: - Remove inter rail diodes - Add Schmitt trigger to add hysteresis to the start-up/down of the DC/DCs. 11V on / 9V off -> Already know the values? Tested with a slow power supply? - Still needed clarification from Rossana about the protections at the 400V/12V DC/DC converter …. Probably they are already there, so not needed at the PBv2 - Use of zener at the output rails? Not needed? Xilinx response to the current power-down sequence of the KINTEX: “our position is that if the customer powers the device down out of order then there is a risk that the IOs can glitch since the supplies powering them are still active As long as the customer is happy to live with this risk (i.e. everything is powering down and a glitch on the IO pins won't matter) then he should be ok to proceed” The question is: Can an IO glitch at the shut-down damage some DOM device? Current in-rush current: What is the current value (without the interrail diodes)? -> Rossana will need it in order to fix the protections at the 400/12 DC/DC output 6

7. Octopusv3 + PMT bases tests: Connect one PMT base to one Octopusv3 prototype and plug it to the CLB prototype -> Test I2C communications to the PMT base Validate Octopusv3 protos On-shore station: Next week setting in the IFIC the broadcast “proof of concept” test bench developed by 7S: 3 WR switches 2 Specs We will try also to test it with one CLBv2 prototype CLBv2 + PBv2.2next prototype 7 CLBv2 prototypes already ordered to MASER 5 PBv2 to be ordered this week 7

8. DFX analysis: Price quotation being prepared by TBP for Octopusv3, CLBv2 and PBv2. ODB++ files from CLBv2 needed. Highly Accelerated Stress Testing: Can help to find weak points. To be applied to only one of the current prototypes once there are available more boards of next series. CLB+PB can be tested together Octopusv3 PMT Base -> can be done already? To be defined: 10 cycles of temperature – visual inspection +functional test – 10 cycles of temperature with 5ºC more in the upper limit (and 5 less in the inferior one) …. Until the first mal functioning on the board appears EMI tests Status? Lead: Remember, it can be used in the soldering and gives better reliability. 8

9. Software for data Analysis (contribution from outside the electronics group): Alex: JPP data analysis software (The same one used for the PPM DOM data analysis – CLBv1) Carmelo: UDP server for CLBv2 frames SPI: needed to implement the images writting on the flash Pattern generator for the Pseudo-Octopus: Implementation on the KC705 on going System test: - Firmware integration in progress - Spec as WR master and as optical ethernet card ready in a linux machine Meeting of Bologna: FIDES result review: CLBv2, PBv2, Octopusv3 and PMT bases Review of the CLBv2, PBv2 and Octopusv3 modifications for the next Proto iteration Preparation of the production: Use of ESS Planification 9