1. Status of CMS CSC upgrade in LS1 Present CSC Status ME 4/2 project ME 1/1 project 5/20/2015 Petr Levchenko NEC 2013, Varna 1

2. CSC Upgrade 5/20/2015 2 Petr Levchenko NEC 2013, Varna

3. 5/20/2015 Petr Levchenko NEC 2013, Varna 3 Total weight : 12,500 t Overall diameter : 15 m Overall length : 21.6 m Magnetic field : 4 Tesla 6 layer multi-wire proportional chambers Cathode Strip Chambers Resistive Plate Chambers MUON ENDCAPS

4. Main goals of CSC Upgrade n Build, install and commossion72 ME4/2 chambers to complete the 4 th station. For the moment YE3 disk uncompleted due to missing outer (1.2<η<1.8) ME4/2 Remove, refurbish, reinstall and commission 72 ME1/1 chambers (1.6<|  |<2.4) n Introduce into the DAQ optical readout electronics and increase number of readout channels (SLink) n Largely extent the LV and HV systems 5/20/2015 Petr Levchenko NEC 2013, Varna 4

5. 5 Schedule driven by YE+4 disk construction with all other activities requiring crane in the shadow (ME1/1 PP) Present Status (Sep 04-Oct 11) 5/20/2015 Petr Levchenko NEC 2013, Varna

6. Recent CMS View 5/20/2015 Petr Levchenko NEC 2013, Varna 6

7. panel storage Incoming parts 5m Loading area 20m Gas Panel cleaning/gluing Strip gluing 25m hand soldering Kit preparatio n 10m Long term gas & HV Electronics assembly Fast site testing 10m 15m 7m 6m 7m Packing Chamber storage area 6m Chamber rack clean Lab 1 clean Lab 2 platform Incoming parts Kit preparation Panel bar gluing Wire wiring, gluing, soldering (Lab 1) Electrical components hand soldering Chamber assembly & test (Lab 2) Long term gas, HV tests Electronics assembly & Fast site test Final inspection packing, storing Chamber production workflow 5/20/2015 7 Petr Levchenko NEC 2013, Varna

8. 5/20/2015 Petr Levchenko NEC 2013, Varna 8 FR4 bar bonding wire winding wire soldering Wire pitch and tension HV testing chamber testingchamber integration components soldering chamber assembly chamber installation

9. ME4/2 schedule (original plan) n Production schedule u A production rate of 1 chamber/week (7 working days) is our target u By February/March 2013 we hope to have built 31 chambers (5 already on YE+3 disk, 2 more ready and 6 in the workflow at b904). u The additional 36 chambers will be ready by March of 2014. l Note: plan to re-use on-chamber electronics from ME1/1 u Our aim is to complete the project on time for installation during LS1, assuming schedule for LS1 will not slip (starting on Nov 17). 1 st endcap2 nd endcap 5/20/2015 9 Petr Levchenko NEC 2013, Varna

10. Achieved chamber production 1 st endcap (30 chambers) 10 Xmas break assuming a rate of 3.3 CSC/month DONE ! Not considering time for chamber long term HV training (8 weeks), electronics integration (2 days) and final testing (3-4 days) 5/20/2015 Petr Levchenko NEC 2013, Varna

11. Chamber production chart 2 nd endcap (36 chambers) 11 Rate = 4 CSC/month ME4/2 chamber factory status: 89% of chambers now assembled 5/20/2015 Petr Levchenko NEC 2013, Varna

12. ME4/2 Electronics Update CSC CFEB ALCT 1 of 24 CFEB 1 of 2 LVDB LV Distribution Board FED Crate in USC55 1 of 5 Anode Front-end Board Cathode Front-end Board Anode LCT Board MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Peripheral Crate on iron disk Slow Control Trigger-Timing-Control Muon Sector Receiver Lev-1 Trigger Trig Motherboard DAQ Motherboard Clock Control Board DDU Board Readout Data RAT aux card (behind) System Layout 5/20/2015 12 Petr Levchenko NEC 2013, Varna

13. CSC ME4/2 project final remarks n The ME4/2 on-chamber and DAQ electronics partially come from the ME1/1 system after refurbishment All board stay unchanged except (UCLA- J. Hauser) ALCT mezzanine boards n Small Spartan-6 FPGA cards u Radiation tested, 100% compatible firmware, passes STEP testing u Originally for ME4/2 only, but low cost  replace on ME1/1 as well n LV system enriched by four Maraton power supplies and LV delivery system (Junction Box) partially recuperated from ME1/1 system n HV system now is the paste copy of station 2.3 with power capacity to supply 72 chambers Spartan-6 vs Virtex-E features: 10x logic 2x speed Low power ~same SEU mitigation options TMB-compatible 5/20/2015 13 Petr Levchenko NEC 2013, Varna

14. ME1/1 Refurbishment and Testing of Boards n All ME-1/1 Chambers have been removed from the Muon Endcap and taken to the SX5 area at the CMS Center n 17 chambers have been refurbished and two have been installed on +YE1 disk l The old electronics already used for the ME-4/2 system u Each refurbished chamber undergoes STEP tests with upgraded readout electronics 14 ME-1/1 ME1/1 SX5 area 5/20/2015 Petr Levchenko NEC 2013, Varna LTT

15. n Many new items u Electronics designs are fully validated u DCFEB, ALCT S6, LVDB7, LVMB7 and PPIB production is complete u >300 of 550 cathode boards (DCFEB) received at CERN n Off-chamber electronics u OTMB are in production u ODMB design is finished, awaiting a Production Readiness Review ME1/1 electronics 5/20/2015 15 Petr Levchenko NEC 2013, Varna

16. ME-1/1 On-Chamber Electronics Upgrade_1 n Remove triple-strip-ganging in ME1/1a region (5  7 CFEB) u Suppress low-p T mis-measured muons u Reduces ambiguities due to combinatorics n ALCT  ALCT(S6): Anode readout board u FPGA Virtex E  Spartan 6 u New, faster FPGA to handle rates n Low Voltage Distribution Board to supply low voltage to on-chamber electronics and Low Voltage Mezzanine Board is the interface between the LVDB and the readout board ODMB, which we use for monitoring and control CSC CFEB ALCT 1 of 24 CFEB LVDB Anode Front-end Board Cathode Front-end Board Anode LCT Board Upgraded Current 5/20/2015 16 Petr Levchenko NEC 2013, Varna

17. ME-1/1 On-Chamber Electronics Upgrade_2 CLK,L1A,JTAG... TMB Path copper Data Path copper Virtex I Trig brd2brd Comparator ASIC 6 Wilkinson ADCs Switch Capacitor ASIC Buckeye Amp/shaper ASIC Coupling/Protection Cathode Front End Boards  Digital Cathode Front End Boards (All OSU design – S.Durkin, B. Bylsma) Virtex 1  Virtex 6 Replace the current analog CFEB with SCA and 16:1 multiplexing ADC by digital design with flash ADC for each channel and digital pipeline storage Optical Data and Trigger Path CLK,L1A,JTAG... TMB Path optical Data Path optical Virtex 6 Trig brd2brd Comparator ASIC Flash ADCs Fully Diff Amps Buckeye Amp/shaper ASIC Coupling/Protection CFEBDCFEB 5/20/2015 17 Petr Levchenko NEC 2013, Varna

18. Low Voltage Distribution Board (LVDB7) n RDMS design (V.Y. Karjavin) n Reviewed in February n Fabrication and assembly in Russia u PCB fabrication complete u Assembly and test have been completed n 72 production boards + spares currently at CERN Terminal block Fixation of LV cable 5/20/2015 18 Petr Levchenko NEC 2013, Varna

19. Low Voltage Mezzanine (Monitor) Board (LVMB7) n UC Davis design (Ray Gerhard) n Performs same functions as previous LVMB but with increased number of channels u interface between ODMB and LVDB boards u Control and monitoring of LVDB power channels n Underwent mini (internal) PRR in May u One FET replaced for rad hardness u Buffer added for temperature monitoring n All PCB’s have been fabricated n 36 assembled production boards at CERN Production LVMB7 with skew clear cable 19 Petr Levchenko NEC 2013, Varna 5/20/2015

20. Patch Panel Interconnect Board (PPIB) n PPIB: active interface board in patch panel to take 2 skew clear cables from OTMB and distribute signals to 7 DCFEBs n Designed by Mike Matveev (Rice) n Prototype arrived in April; production completed and all board delivered to CERN n Uses existing skew clear cables to connect to ODMB n Uses new cables to connect PPIB to DCFEBs 2 skew clear cables to ODMB 7 new cables to DCFEBs 5/20/2015 20 Petr Levchenko NEC 2013, Varna

21. ME-1/1 Readout Electronics Upgrade n Optical Trigger Mother Board (OTMB). UCLA – J. Hauser u Replaced Mezzanine card. TAMU – J Gilmor l Virtex 6 FPGA enhances our capabilities l memory & speed for improved trigger logic l Use 7 multi-gigabit serial links for data from DCFEBs u New Base Board l A new front panel to make room for optical links l Modification specifically targets improvement in power distribution l Full backwards compatibility is maintained 5/20/2015 21 Petr Levchenko NEC 2013, Varna

22. ME-1/1 Readout Electronics Upgrade Optical Data acquisition Mother Board (ODMB) UCSB, NE u Optical Transceivers u New Virtex-6 to handle the fiber optic data and optical transmission for 7 DCFEBs 5/20/2015 22 Petr Levchenko NEC 2013, Varna

23. System Test of Endcap Peripheral Crate and Chamber Electronics (STEP Tests) n A comprehensive tests of the chambers which can help detect problems with connectivity, noise, and electronics firmware n Set of tests below are performed on all me-1/1 chambers being refurbished n All CSC chambers installed on the muon endcap have undergone these tests STEP tests Slow Control Anode Front End Board Threshold and Analog Noise test Anode Front End Board Noise test Anode Front End Board Time-delay verification Pipeline Depth test Digital Cathode Front End Board Noise test Digital Cathode Front End Board Connectivity test Digital Cathode Front End Board DAQ-Path Calibration: Pulse Response and Cross Talks Digital Cathode Front End Board DAQ-Path Calibration: Amplifier Gain Digital Cathode Front End Board Comparator Thresholds and Analog Noise Digital Cathode Front End Board Left/right Comparator Logic test ALCT self-trigger on cosmic test High-statistics cosmic test Chamber gain map 5/20/2015 23 Petr Levchenko NEC 2013, Varna

24. Some items… n ME1/1 electronics upgrade invoke deep changes in LV system n LV system enriched by eight Maraton power supplies and LV delivery system (Junction Box) was completely redesigned by S.Lusin and produced by Wisconsin and now in CERN n In order to prove high reliability new CSC electronics special Low Voltage Test stand (LTT)has been built in SX5 test area. It has capacity to run six chambers in the same time n * CSC DAQ hardware in USC - number of readout channels (SLink) increased from 8 to 36 to better cope with higher rates and new chambers - chamber grouping modified for better load balancing * CSC computers - upgrading to more powerful server PCs for detector control and VME communication - new interface cards for VME communication * CSC software - adapting to the new electronics on the innermost 72 chambers. configuration. control and monitoring (+DCS). data format - updating operating system to SLC 6 or 7 (based on Red Hat EL 6 or 7) - updating to latest CMS online software framework - expanding the scope of expert system - exploiting parallel processing - consolidating applications 5/20/2015 Petr Levchenko NEC 2013, Varna 24

25. n Very intense in Oct-Nov for + side endcap: u ME4/2 starts Oct. 7, want 24/7 operation for commissioning u ME1/1 starts Oct. 17 Installation schedule 5/20/2015 25 Petr Levchenko NEC 2013, Varna

26. Summary n CSC Upgrade on it straight way, but still lot of work to do…. n ME4/12 project is close to final stage. n ME1/1 refurbishing goes well. n In spite of some delay CSC installation going to happened soon 5/20/2015 26 Petr Levchenko NEC 2013, Varna