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COMPARATIVAS COP8 vs. PIC. COP8SAC Diagrama en Bloques Interrupt 16 bit Timer T1 Instr. Decoder ALU SO SK SI (E6-E7) (EA-ED) ROM Ad. RAM Ad. EPROM 4 K.

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Presentation on theme: "COMPARATIVAS COP8 vs. PIC. COP8SAC Diagrama en Bloques Interrupt 16 bit Timer T1 Instr. Decoder ALU SO SK SI (E6-E7) (EA-ED) ROM Ad. RAM Ad. EPROM 4 K."— Presentation transcript:

1 COMPARATIVAS COP8 vs. PIC

2 COP8SAC Diagrama en Bloques Interrupt 16 bit Timer T1 Instr. Decoder ALU SO SK SI (E6-E7) (EA-ED) ROM Ad. RAM Ad. EPROM 4 K Bytes (0-3FFF) MAR PC FEATURE CORE RAM 128 Bytes Clock Halt / Idle Wake Up Reset I/O Ports G 8-bits L 8-bits D 8-bits F 8-bits C 8-bits (D4-D6)(D0-D2)(D8-DA)(DC)(94-96) Watch Dog Logic (C7) Multi Input Wake Up (C8-CA) 16 Bit Idle Timer T0 A B X SP PSW CNTRL (FE) (FC) (FD) (EF) (EE) S (FF) (E9) Micro- Wire/ Plus Modified Harvard Architecture

3 Comparativa de características COP8 vs. PIC16C5x

4 Benchmarks Transferencia de 5 bytes de RAM a RAM Suma Binaria de 4 bytes Resta BCD de 8 Dígitos Uso de los Puertos de I/O I/O Serial + Acceso a tabla Búsqueda de 3 chars (string) en una tabla de 200

5 Diagrama en bloques del sistema COP8 PIC DAQ Timer Gate Reset Selección de benchmark Gate Reset

6 START STOP Benchmark #1 Cargar registros indice Copiar byte origen a destino 5 bytes ? Incrementar los indices NO SI Código fuente...

7 START STOP Benchmark #2 Cargar registros indice A i <— B i + A i 4 bytes ? Incrementar los indices NO SI Código fuente...

8 START STOP Benchmark #3 Cargar registros indice Restar dos digitos y corregir 4 bytes ? Incrementar los indices NO SI Código fuente... Res. Neg.? SI NO Complementar el resultado

9 START STOP Benchmark #4 Cargar puntero para tabla Char 3 ? Incrementar puntero Char 1 ? Char 2 ? SI NO Fin tabla ? SI NO STOP

10 START STOP Benchmark #5 Leer puertos (P1, P2) P1 = P2 ? NO SI P1 > P2 ? NO SI P3 <— 9 P1 <— P2 P3 = l_P1 | h_P1

11 START STOP Benchmark #6 Cargar contadores Leer direccion y dato1 (serie) 100 bytes ? dato2 <— [dirección] NO SI Enviar dato1 + dato2

12 Código Fuente #1 Benchmarks COP8PIC START LD B, #14 ; 1 LD X, #50 ; 2 BM1LOOP: LD A, [B+] ; 1 X A, [X+] ; 1 IFBNE #3 ; 1 JP BM1LOOP ; 1 STOP START MOVLW 5 MOVWF B1CNTR MOVLW 10 B1LOOP:MOVWF B1BASE MOVWF FSR MOVF INDF, W MOVWF B1TEMP MOVLW 5 ADDWF FSR, F MOVF B1TEMP, W MOVWF INCF B1BASE, F DECFSZ B1CNTR, F GOTO B1LOOP STOP

13 Código Fuente #2 Benchmarks COP8PIC START LD B, #10 ; 1 LD X, #20 ; 2 RC ; 1 BM2LOOP:LD A, [X+] ; 1 ADC A, [B] ; 1 X A, [B+] ; 1 IFBNE #14 ; 1 JP BM2LOOP ; 1 STOP START MOVLW 4 MOVWF B2CNTR MOVLW 10 MOVWF B2BASE BCF STATUS, 0 B2LOOP:MOVF B2BASE, W MOVWF FSR MOVF INDF, W MOVWF B2TEMP MOVLW 4 SUBWF FSR, F MOVF B2TEMP, W ADDWF INDF, F MOVLW 4 ADDWF FSR, F INCF B2BASE, F DECFSZ B2CNTR, F GOTO B2LOOP STOP

14 Código Fuente #3 - COP START LD B, #14 ; 1 LD X, #20 ; 2 SC ; 1 BM3LOOP: LD A, [X+] ; 1 X A, [B] ; 1 SUBC A, [B] ; 1 DCOR A ; 1 X A, [B+] ; 1 IFBNE #2 ; 1 JP BM3LOOP ; 1 IFNC ; 1 JP BM3NEGR ; 1 RC ; 1 STOP BM3NEGR:SC ; 1 LD B, #14 ; 1 BM3LUP: CLR A ; 1 SUBC A, [B] ; 1 DCOR A ; 1 X A, [B+] ; 1 IFBNE #2 ; 1 JP BM3LUP ; 1 SC ; 1 STOP

15 Código Fuente #3 - PIC Benchmarks START MOVLW. 4 MOVWF B3CNTR MOVLW 0x20 MOVWF B3BASE BSF STATUS, 0 B3LOOP:MOVF B3BASE, W MOVWF FSR MOVF INDF, W MOVWF B3TEMP MOVLW. 4 SUBWF FSR CALL B3CORR MOVLW. 4 ADDWF FSR DECFSZ B3CNTR GOTO B3LOOP BTFSS STATUS, 0 GOTO B3NEGR BCF STATUS, 0 STOP goto $ B3NEGR: MOVLW. 4 MOVWF B3CNTR MOVLW 0x20 MOVWF B3BASE BSF STATUS, 0 B3LUP: MOVF B3BASE, W MOVWF FSR MOVF INDF, W MOVWF B3TEMP CLRF INDF CALL B3CORR DECFSZ B3CNTR GOTO B3LUP BSF STATUS, 0 STOP goto $ B3CORR:CLRF B3FLAG MOVF B3TEMP, W SUBWF INDF CLRF B3TEMP BTFSC STATUS, 0 GOTO B3BYP1 MOVLW 60H ADDWF B3TEMP B3BYP1:BSF B3FLAG, 0 BTFSC STATUS, 1 GOTO B3BYP2 MOVLW 06H ADDWF B3TEMP B3BYP2: MOVF B3TEMP, W BSF STATUS, 0 SUBWF INDF BTFSC B3FLAG, 0 BCF STATUS, 0 INCF B3BASE RETLW 0

16 COP8 RAM Organization F0-FF S = FF 80-FF 70-7F 00-6F Unused (Reads as all ones) On-Chip RAM (64 Bytes) Unused (Reads as all ones) (S) = 00 (S) = 01(S) = XX 017F 013F 0100XX00 XX7F SegmentNSegmentN Segment 1Segment 1 Segment0Segment0 BaseAddressRangeBaseAddressRange If bit #7 of an address = 0, S is used to extend base address range, example shows a device with 192 bytes RAM

17 COP8 Data Memory Organization F0-FFOn Chip User RAM, B&X ind. memory pointers, Stackpointer. Some special instr. (DRSZ) support only in this memory area (16 bytes) E0-EFOn Chip Function Registers (Timer1, MICROWIRE/PLUS, PSW, CNTRL-Reg., etc.) D0-DFOn Chip I/O Registers 80-CFOn Chip Function Registers (Timers, Multi-Input Wakeup, A/D, UART, etc.) Unused locations read undefined data 70-7FUnused RAM Address Space (reads all ones) 00-6FOn Chip User RAM (112 Bytes)

18 COP8 Interrupt Structure

19 VIS Flowchart

20 COP8 Port Structure Pin INTERNAL BUSINTERNAL BUS Data Register Configuration Register Data Register Bidirectional I/O Port Output-Only Port

21 HALT mode IDLE mode Multi-Input-Wake-Up (MIWU), to exit power save modes via any of up to eight external events HALT mode IDLE mode Multi-Input-Wake-Up (MIWU), to exit power save modes via any of up to eight external events Power Save Modes

22 HALT Mode HALT can be disabled via OTP configuration register or mask option All activities stopped except clock monitor –Enter HALT mode Setting the G7 data bit (program) –Exit HALT mode RESET Low to high transition on CKO Multi-Input Wakeup HALT can be disabled via OTP configuration register or mask option All activities stopped except clock monitor –Enter HALT mode Setting the G7 data bit (program) –Exit HALT mode RESET Low to high transition on CKO Multi-Input Wakeup

23 IDLE Mode All activities stopped except –Oscillator –WATCHDOG logic –Clock monitor –IDLE timer (T0) Enter IDLE Mode by –Setting the G6 data bit (program) Exit IDLE Mode –Reset –Multi-Input Wakeup –T0 13-bit toggles All activities stopped except –Oscillator –WATCHDOG logic –Clock monitor –IDLE timer (T0) Enter IDLE Mode by –Setting the G6 data bit (program) Exit IDLE Mode –Reset –Multi-Input Wakeup –T0 13-bit toggles

24 Instruction Set - Addressing Modes Direct:LD A, 05 Register IndirectX A, [B] Register Indirect withX A, [B±] Post Inc / DecX A, [X±] ImmediateLD A, #05 Immediate ShortLD B, #07 Indirect from Program MemoryLAID Jump RelativeJP 0A Jump AbsoluteJP 013F Jump Absolute LongJP 313F Jump IndirectJID Direct:LD A, 05 Register IndirectX A, [B] Register Indirect withX A, [B±] Post Inc / DecX A, [X±] ImmediateLD A, #05 Immediate ShortLD B, #07 Indirect from Program MemoryLAID Jump RelativeJP 0A Jump AbsoluteJP 013F Jump Absolute LongJP 313F Jump IndirectJID

25 Instruction Set - Types Arithmetic & Logic –ADD, SUBC, AND, OR, XOR A & C Specific –CLRA, SC, RC Transfer of Control –JMP, JSR, RET, NOP Memory Transfer –LD, X Conditionals Arithmetic & Logic –ADD, SUBC, AND, OR, XOR A & C Specific –CLRA, SC, RC Transfer of Control –JMP, JSR, RET, NOP Memory Transfer –LD, X Conditionals

26 Instruction Set - Arithmetic ADD ADC SUBC AND OR XOR ANDSZ DRSZ ADD ADC SUBC AND OR XOR ANDSZ DRSZ

27 Instruction Set - Accumulator and Carry CLRA INCA DECA LAID DCOR RRCA RLCA PUSHA CLRA INCA DECA LAID DCOR RRCA RLCA PUSHA POPA SWAPA SC RC IFC IFNC

28 LAID - instruction LAID Load value to Accumulator (0-256) Accumulator updated from table. ROM Table LAID EA

29 Instruction Set - Transfer of Control JMPL JMP JP JSRL JSR JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP

30 Instruction Set - Memory Transfer LD A, address LD B, immediate LD Mem, immediate LD Reg, immediate X A, address LD A, address LD B, immediate LD Mem, immediate LD Reg, immediate X A, address

31 Conditionals IFEQ IFNE IFGT IFBNE IFBIT IFC IFNC IFEQ IFNE IFGT IFBNE IFBIT IFC IFNC

32 Three Wire Serial Connection Bidirectional Flexible Frame Transmission Programmable Transmission Speed Master/Slave Mode Short Message Length Comparable Small Circuit Three Wire Serial Connection Bidirectional Flexible Frame Transmission Programmable Transmission Speed Master/Slave Mode Short Message Length Comparable Small Circuit MICROWIRE/PLUS™

33 MICROWIRE/PLUS Circuit Block Diagram PSW CLK Select Divider TC1TC2TC3TRUNMSELIEDGSL1SL0 Bit 7Bit 0 Bit 7Bit 0 Instruction Clock SO SI SK SIOR Internal Data BusInternal Data Bus BUSY CNTRL

34 MICROWIRE/PLUS Example COP8 (Master) COP8 (Slave) A/DE2E2 PLL LCD Driver DODICLKDODICLKDICLKDICLK SI SO SK SI SO SK Chip Select Lines

35 COP8 Timer Structure T1RA Timer T1 T1RB IDLE Timer Timer T0 SEL tCtC T1B T1A tCtC Internal Data BusInternal Data Bus

36 IDLE Timer (T0) WATCHDOG Logic Down Counter (T0) T0PNDT0EN IDLE Chip Clock tC ICNTRL Register Multi-Input Wake-Up Logic Interrupt G6 Data Bit SR Internal Data Bus Q


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