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1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far.

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Presentation on theme: "1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far."— Presentation transcript:

1 1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far is called a random logic approach and is a complicated logic design exercise. Each design is unique and depends upon the instruction set and the internal arrangements. The method does not lend itself to modifications afterwards.

2 2 Microprogrammed Approach Wilkes (in 1951) suggested an alternative approach for control unit design called microprogramming. Each elementary step is encoded into a binary pattern in much the same way as machine instructions, and held in a memory within the control unit. Not widely adopted until the 1960’s but particularly convenient for complex instruction sets. Generally not used in simple RISC designs. Wilkes, Maurice (1951). "The Best Way to Design an Automatic Computing Machine". Report of Manchester University Computer Inaugural Conference. pp. 16–18. Confident! Note 1951. This material is now historical and given for completeness.

3 3 Microprogrammed Control Unit Design Operations for each state encoded in binary in an instruction known as a microinstruction (a small instruction) Each microinstruction will cause the signals necessary to transfer data from one place to another in the processor, and activates functional units if necessary for the operation. Microprogram – A list of microinstructions for each machine instruction. Microprogram held in a very high speed memory called the control memory within the control unit of the processor.

4 4 Microprogrammed Control Unit - Basic Concept

5 5 Microinstruction Formats 1. Horizontal Microinstruction Format One bit for each possible signal that might need to be generated by any microinstruction - leads to the fastest execution: Example MAR  PC Requires d bits if there are d possible destinations plus s bits if there are s possible sources.

6 6 2. Vertical Microinstruction Format Mutually exclusive operations grouped together and encoded in binary. Reduces number of bits in microinstruction. Each vertically encoded field needs a decoder:

7 7 Example Suppose there were up to 15 possible sources and destinations (PC, MAR, MDR, IR....). Four bits needed to specify which one: EncodingDestinationSource 0000NoneNone 0001RdRs1 0010.Rs2 0011IR. 0100.IR 15-0 0101.IR 25-0 0110.0 (zero) 0111R314 (constant) 1000PCPC 1001MDRMDR 1010MARMAR... This is just an example of how it could be encoded, but this will be used later. One pattern for no signals Various parts of IR Used in Branch Used to increment PC

8 8 Vertical Format Microinstruction Encoding Example MAR  PC

9 9 More Complex Operations Vertical encoding typically used to select arithmetic functions, etc. Example PC  PC + IR 25-0 Need two sources, destination and arithmetic operation specified in microinstruction:

10 10 Possible ALU function Encoding EncodingALU function 0000None (ALU out = ALU in1 ) 0001Add 0010Subtract 0011Multiply 0100Divide 0101AND 0110OR 0111Shift left 1000Shift right 1001. Again this is just an example of how it could be encoded, but it will be used later.

11 11 Example Encoded Microinstruction PC  PC + IR 25-0

12 12 Microinstruction Sequencing Need a mechanism to specify next microinstruction to be executed. Original (Wilkes) method was to hold the address of the next microinstruction in a field within the microinstruction (so-called four- address instruction format):

13 13 Microprogram counter More convenient approach for microinstructron sequencing is to use a microprogram counter to hold the address of the next microinstruction just as machine instruction sequencing uses a program counter. Then simply increment the microprogram counter after each microinstruction is fetched in preparation for fetching the next microinstruction.

14 14 Branch Microinstructions Needed for implementing branch machine instructions. Also useful for implementing a complex machine instruction with microinstructions. Original Wilkes method: Used a microinstruction with two “next microinstruction” addresses, one for identifying state if condition true and one for identifying the state if the condition is false. In our case with a microprogram counter: - Only need to hold branch target in the “next microinstruction” address field in microinstruction. The microprogram counter holds the address of next sequential microinstruction. In either case, logic to select one address depending upon whether the condition had been met.

15 15 Branch Microinstructions In our design, need to implement:

16 16 BL instruction State 21 Rs1 - 0 (compare Rs1 against zero) if (negative) goto state 22 else goto state 0 This can be simplified by arranging state 22 to be immediately after state 21 in the microprogram. Then state 21 reads: Rs1 - 0 (compare Rs1 against zero) if (positive) goto state 0 where condition is the opposite to that previously. All branch sequences are similar.

17 17 Microinstruction with Conditional Branch Operations Example Again this is just an example of how it could be encoded, but it will be used later.

18 18 Conditional Branch Microinstruction Example Rs1 - 0; if (negative) goto branch location Using previous encoding. Number of bits in branch address depends upon maximum size of the control memory. Can also use two different formats, one for non-branch and one for branch to reduce wasted space in microinstruction (first bit specifies format).

19 19 Other Operations Other operations include: Memory Read/Write Could have one bit for either:

20 20 Memory Write [MAR]  MDR Memory Read MDR  [MAR]

21 21 Fetch Cycle Could be done in microcode or by special hardwired logic. Suppose done in microcode starting at location 0 in control memory: Control memoryMicroprogram locationDestFnSrc1Src2WRCond Br addr. T 0 :MAR  PC0000101000001000000000 000 0... 0 T 1 :MDR  [MAR]0001000000000000000001 000 0... 0 T 2 :IR  MDR0010001100001001000000 000 0... 0 T 3 :PC  PC + 40011100000011000011100 000 0... 0 Subsequently, we will assume step T 3 done using separate logic at same time as step T 2. Final Microprogram

22 22 Execute Cycle Selecting Execute Microcode At the end of fetch cycle, need to select the start of the microprogram (microcode) for the specific fetched machine instruction. Generally, the op-code of the machine instruction can be used. The fetched machine instruction will be in the instruction register (IR) at this time.

23 23 Fetch Mapping ROM Convenient to use a read-only memory (ROM). Opcode used to select location in mapping ROM. Contents of addressed location holds address of microinstruction in control memory:

24 24 Example Suppose opcode pattern is 000110, and location 120 in control memory holds first microinstruction of microprogram to execute machine instruction.

25 25 Selecting Execute Microcode Need to have the step: “branch to location specified by op-code mapping ROM” at the end of fetch cycle. We shall choose to provide new field called here select, defined as follows: select 00Next address given by microprogram counter (i.e. default for sequential execution) 01Next address given by op-code mapping ROM 10Next address given by branch address field of microinstruction if condition exists (i.e. for branch microinstructions) Pattern 11 available and could be used to implement microinstruction subroutines, see later.

26 26 Next Address Select Field Final microinstruction format for our design. There could be other miscellaneous operations.

27 27 Microprogrammed Control Unit Design

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30 30 Alternative Designs -- Clearly there are many alternative designs. We have used mainly vertical encoding but this does lead to slower operation. Often horizontal encoding is used with very long microinstruction lengths (100 bits or more).

31 31 Questions

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