1. Hervé Lebbolo, François Rossel, Aurore Savoy-Navarro LPNHE-Universités de Paris 6&7 TOPICS: Main parameters of the Si-Envelope Front-End Issues: Long shaping time Proposed F.E schema Digitization on detector F.E DAQ & Trigger: very preliminary ideas CERN, February 6th 2003

2. The Si-Envelope components: due to their location the functions of each piece of the Si-envelope may (slightly) differ SIT SET FTD Si-FCH

3. As in AMS Si-tracker, we propose to build long ladders made of N sensors bonded to each other F.E. electronics connector

4. The Si-envelope components in a few numbers: Si-envelope Component Items Total Number Si-FCH (XUV)Nb of layers Nb of ladders, 4 sensors Nb of ladders, 5 sensors Nb of ladders, 6 sensors Nb of RO channels/endcap Power dissipation 4 XU + 2 VV 192 480 288 983,000 393 Watts SETNb of layers Nb of ladders Nb of RO channels Power dissipation 2 1-sided + 1 2-sided 4480 2,293,760 920 Watts SITNb of layers Nb of ladders Nb of RO channels Power dissipation 2 2-sided 38 + 94 =132 270,336 110 Watts

5. Proposed Si-FCH DESIGN Modularity: ladders with 4,5or 6 sensors 4 Quadrants 4 XUV made of 6 2-sided sensors: 4 XU & 2 VV XUVVUXXUVVUX

6. The Front-End Electronics issues Starting point: the AMS electronics R.O. System Proposed Front-End design: the basics The Long shaping time Digitization on the detector F.E. ?

7. Starting point: the AMS Si-tracker Readout system (With particular thanks to G. Ambrosi, Ph. Azzarello, W.Lusterman and the ETH-Zurich, Geneva U.& Peruggia U. AMS teams for their support) Tracker Front-EndTracker Data Reduction Input Capa = 33 –72 pF VA_hdr/AMS64: 64 charge ampli+ CR-RC shaper+ S&H + 64 ch connected to voltage-current output buffer by analog mux  seq. RO@ up 10 MHz Measured ENC= (350+4/pFxC) electrons at 6 µsec peaking time 12 bit low power A/D (CLC949), as need: large dynamic range +/- 100 MIPs dig. @ 5 MHz A/D coupled to DSP via FPGA (Xilinx XC4013)= buffer for up to 3 evts & sequencer for FE timing signals and synchro data transfer. 16 bits-DSP @30MHz for calib and data compression

8. AMS2 : new improved Readout system New Front End: New hybrid: VA_hdr9a, 0.8µ Internally generated biases, internal calib capa Nominal gain 1.4 µA/fC Nominal peaking time 6 µsec ENC=(300 + Cdet x 5/pF)e-  Good gain stability & small pedestal spread New readout scheme: Simplified and HCC (Hybrid Control Circuit)  Minimize digital cable line  Control daisy chain of VA  Increase system reliability  Follows space rules By courtesy of G. Ambrosini

9. Currently building a 7-sensor ladder with AMS technique (i.e. using AMS sensors) and bonding them together thus variable length for test : L = N x 30 cm long This long ladder will be ready by Feb 20th equipped with FE electronics à la AMS (VA Preampli) or direct access at the µcrostrip output. Also starting simulation studies on new FE+RO possible designs (Ongoing similar studies at UC Santa Cruz, on a 2 m long ladder) Lab test bench: @LPNHE-Paris Long ladder prototype Sensors: 70.0x40.1 mm2 300 µm depth 110µm/208µm RO pitch p(junction side) n(ohmic side)

10. Proposed F.E. Readout chain: very preliminary ideas 512 channels/ladder 2560 channels/drawer A/D=0.35µtechno, 8 bits 1MHz clock, 1.2mW

11. What infos do we need from the Si-tracker? 1) Detector occupancy? Will be different according to the detector location SET: preliminary studies  occupancy  1 % SIT, FTD or Si-FCH should have higher occupancies (higher backgrounds)  SPARSIFICATION on detector F.E. ? 2) Double & Multiple hit rates ? Thus ambiguities must be estimated 3) Pulseheight info (Q) needed? Yes if cluster centroid (  8 bit A/D ?) 4) Timing information ? R.O both ends of the long ladder? 5) Pedestal substraction on board? 6) DSP-like processing for eventual cluster algorithm and eventual fastrack processing algorithm at what level in the electronic chain ??? 7) Power dissipation studies: preliminary results  don’t seem to be a major issue (more detailed ongoing studies) All these issues must be studied with electronics and physics &/or detector performance simulations and tests on the test bench (just starting...)

12. Output of the signals: very preliminary proposal

13. DAQ & intermediate ‘trigger’: very preliminary ideas Based on the current experience with the trigger system related to the tracking system in CDF, we are foreseeing to study a Fastrack ‘trigger’ (or realtime processing) system that could be used to 1) Do a fast clustering and determine in realtime the cluster centroid 2) Do a fast tracking for stiff tracks (above 1 or 1.5 GeV/c momentum) with the overall Si tracking information, i.e. starting with the SIT + SET and then linking to the µvertex informations And similarly in the forward region, perform a track segment reconstruction in FTD and Si-FCH, separately and possibly link them.

14. Concluding remarks Our main efforts are currently focusing on developing the Lab test bench including the construction of a long ladder prototype with variable length and different possible Front-Ends The starting scheme = AMS FE and RO system Also looking for compatibility with the general RO & DAQ frame of the LC experiment In parallel, both electronics and physics + detector performances simulation studies are/will be undergoing for studying new FE and RO schemes and algorithms to eventually include in the RO chain for more sophisticated realtime processing of data (cluster centroid, fast tracking etc…). Use of present CDF experience and ongoing LHC developments. More to come in the next months (PRC submission )