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1 Lecture 7 Integer Arithmetic Assembly Language for Intel-Based Computers, 4th edition Kip R. Irvine

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2 Integer Arithmetic n Shift and Rotate instructions n Sample Applications n Extended Addition and Subtraction n Multiplication and Division n ASCII and Packed Decimal Arithmetic

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3 Shifting and rotating n Shifting: The bits a shifted left or right. Some bits may be lost. Example: Shift 00001101 1 bit right Added 00000110 Lost n Rotating: The bits shift out of one end of the data are placed at the other end of the data so nothing is lost. Example: Rotate 10001101 2 bits to the left: 00110110

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4 SHL (Shifting bits to the left) n To shift 1 bit to the left we use: SHL dest(reg/mem),count(imm8/CL) u the msb (most significant bit) is moved into CF (so the previous content of CF is lost) u each bit is shifted one position to the left u the lsb (least significant bit) is filled with 0 u dest can be either byte, word or dword n Ex: mov bl,82h ; BX = _____ shl bl,1 ; BX = _____, CF = __ (only BL and CF are changed)

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5 Shifting bits to the left 101000000 BLCF After SHL BL, 1 Before 1 0 0 0 0 0 1 0 0

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6 Shifting multiple times to the left n SHL affects SF, PF, ZF according to the result n CF contains the last bit shifted from the destination n OF = 1 iff the last shift changes the sign bit u mov bh,0B2h ;BH = 1011 0010b shl bh, 1 ;BH = ______b, CF=__, OF=__ shl bh, 2 ;BH = ______b, CF=__, OF=__ n Overflows are signaled only for the last bit shifted

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7 Fast Multiplication n Each left shift multiplies by 2 the operand for both signed and unsigned interpretations. Ex: mov al,4 ;AL = 04h = 0000 0100b = 4 shl al,1 ;AL = 08h = ______________b = ____ shl al,2 ;AL = 20h = ______________b = ____ mov bl,-1 ;BL = FFh = ______________b = ____ shl bl,3 ;BL = F8h = ______________b = ____

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8 Fast Multiplication n Cycles Instruction 8088 80486 Pentium SHL reg, 1 2 3 1 SHL reg, immed - 2 1 SHL reg, CL 8 + 4n 3 4 MUL reg byte 70-77 13-18 11 word 118-133 13-26 11 doubleword N/A 13-42 10 n Source: 8088, 80486: Reference Microsoft MASM, Microsoft Corporation, 1992 n Source: Pentium: Pentium.txt, MASM 6.13 update, Microsoft Corporation, 1993

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9 Fast Multiplication n Multiplication by shifting is very fast. Try to factor your multiplier into powers of 2: u AX * 36 = AX * (32 + 4) = AX*32 + AX*4 u So add (AX shifted by 5) to (AX shifted by 2) That is, we might replace a multiply by 36 instruction by copy AX to BX shift AX left 5 bits (32 * AX) shift BX left 2 bits (4 * AX) add BX to AX (36 * AX)

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10 Fast Multiplication Multiplication using shifts on 8088 mov BX, AX mov CL, 5 shl AX, CL shl BX, 1 shl BX, 1 add AX, BX 8088 cycles 2 4* 8+4*5 = 28* total = 41 2 2 3 4 total = 113-133 117-137 * Replace by 5 shl AX, 1 commands total = 19 mov CX, 36 mul CX Normal multiplication

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11 Fast Multiplication Multiplication using shifts on 486 Pentium mov BX, AX shl AX, 5 shl BX, 2 add AX, BX 486 cycles Pentium 1 1 2 1 2 1 1 1 Total 6 4 13-26 11 imul AX, 36 Normal multiplication

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12 SHR (Shifting bits to the right) n To shift to the right use: SHR dest(reg/mem),count(imm8/CL) F the msb of dest is filled with 0 F the lsb of dest is moved into CF n Each single-bit right shift divides the unsigned value by 2. Ex: u mov bh,13 ;BH = ______b = 13 u shr bh,2 ;BH = ______b = 3 (div by 4), CF = 0 u (the remainder of the division is lost)

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13 Arithmetic Shift SAR n Is needed to divide the signed value by 2: SAR dest(reg/mem),count(imm8/CL) F the msb of dest is filled with its previous value (so the sign is preserved) F the lsb of dest is moved into CF

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14 Arithmetic Shift n mov ah,-15 ;AH = 1111 0001b sar ah,1 ;AH = ________________b = -8 the result is rounded down (-8 instead of -7…) n In contrast, shr ah,1 gives ____________b = 78h n SAL is the same as SHL It is just interpreted as being for signed arithmetic

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15 Rotate (without the CF) n ROL rotates the bits to the left (same syntax) u CF gets a copy of the original msb n ROR rotates the bits to the right (same syntax) u CF gets a copy of the original lsb n CF and OF reflect the action of the last rotate

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16 Examples of ROL and ROR mov ah,40h ;ah = 0100 0000b rol ah,1 ;ah = 1000 0000b, CF = 0 rol ah,1 ;ah = 0000 0001b, CF = 1 rol ah,1 ;ah = ____________b, CF = ___ mov ax,1234h ;ax = 0001 0010 0011 0100b = 1234h ror ax,4 ;ax = 4123h ror ax,4 ;ax = 3412h ror ax,4 ;ax = 2341h

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17 Rotate with CF n RCL rotates to the left with participation of CF n RCR rotates to the right with participation of CF

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18 Ex: Reversing the content of AL n Ex: if AL = 1100 0001b, we want to reverse the order of the bits so AL = 1000 0011b mov cx,8 ;number of bits to rotate start: shl al,1 ;CF = msb of AL rcr bl,1 ;push CF into msb of BL loop start ;repeat for 8 bits mov al,bl ;store result into AL

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19 SHLD/SHRD Instructions n SHLD: SHLD dest, Source, count(imm8/CL) F Shift a dest. a given number of bits to the left F The bit positions opened up by the shift are filled by the msb of the source operand n SHRD: SHRD dest, Source, count(imm8/CL) F Shift a dest. a given number of bits to the right F The bit positions opened up by the shift are filled by the lsb of the source operand

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20 SHLD/SHRD Instructions n Formats: SHLD/SHRD reg16, reg16, imm8/CL mem16, reg16, imm8/CL reg32, reg32, imm8/CL mem32, reg32, imm8/CL n Examples:.data lval word 923Bh.code mov ax,0AC36h mov bx, 786Ah shld lval, ax, 8 shrd bx, ax, 4 923BAC36 786A 3BACAC36 6786 lval AX AX BX

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21 Application: Binary Output n To display the number in BX in binary: MOV AH,2 ;display MOV CX,16 ; 16 chars START: ROL BX,1 ;CF gets msb JC ONE ;if CF =1 MOV DL,’0’ ;print '0' JMP DISP ONE: MOV DL,’1’ ;print '1' DISP: INT 21h ;print

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22 Multiplying with shifts and adds n Some early CPUs lacked hardware multiply n Solution: Shift and add routines n Advantage: "Cheaper" n Disadvantage: Slow n Algorithm show here is simple, faster ones are available. Neat feature: it calculates a double width product using single width operations except for rotating

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23 Multiplying with shifts and adds n Algorithm: Assumes BL contains multiplicand DL contains multiplier 1. Initialize Clear accumulator AX Put 8 in CX 2. Repeat 8 times (once per bit of multiplier) Shift DL right by 1 bit into CF If CF = 1, Add BL to AH with carry in CF Rotate AX (include CF) The result is in AX.

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24 Multiplying with shifts and adds n Multiply PROC XOR AX, AX MOV CX, 8 Repeat1: SHR DL, 1 JNC Lskip ADD AH, BL LSkip: RCR AX, 1 LOOP Repeat1 RET Multiply ENDP

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25 Multiplying with shifts and adds n 4 bit example 0110 * 1010 DL = 1010 0101 0010 shift CF = ? 0 1 BL = 0110 0110 0110 AX = 0000 0000 0110 0000 add CF = 0 AX = 0000 0000 0011 0000 rotate CX = 4 3 2

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26 Multiplying with shifts and adds u 4 bit example 0110 * 1010 continued DL = 0001 0000 shift CF = 0 1 BL = 0110 0110 AX = 0111 1000 add CF = 0 AX = 0001 1000 0011 1100 rotate CX = 1 0

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27 Extended Addition n Question: Early microcomputers were only 8 bit machines. How could you add 16 or 32 bit integers? On 16 bit machines how do you add 32 bit integers? n Intel solution: ADC dest, source Usage rules are the same as for ADD n dest = dest + source + carry flag n Example AX = 1000h, BX = 20, CF = 1 ADC AX, BX ; AX =_______h

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28 Add dWord2 to dWord1 n dWord1 dd ? dWord2 dd ? … (Using byte arithmetic) mov al, byte ptr dWord2 add byte ptr dWord1, al mov al, byte ptr dWord2+1 adc byte ptr dWord1+1, al mov al, byte ptr dWord2+2 adc byte ptr dWord1+2, al mov al, byte ptr dWord2+3 adc byte ptr dWord1+3, al

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29 Extended Subtraction n SBB - subtract with borrow n SBB destination, source destination = destination - source - CF Usage: just like ADC AX = 1000h, BX = 20, CF = 1 SBB AX, BX ; AX =______h;

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30 Extended Subtraction n Example: Calculate X = X - Y where X and Y are double words on a 8088 with only 16 bit registers n X dd 1023321 Y dd 342232 … mov ax, word ptr Y sub word ptr X, ax mov ax, word ptr Y+2 sbb word ptr X+2, ax

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31 Integer Multiplication: A Consideration n Question: if we multiply a n bit number by another, how long could the product be? Example n = 4 1111 x 1111 1111 1111 1111 1111 11100001 n The product of two n bit numbers can be 2n bits long

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32 Integer Multiplication - the problem n The product of two n bit numbers can have up to 2n bits n In high level languages, the product of two n bit numbers can have at most n bits n Question: If you designed the hardware, would the product of two n bit numbers have n bits or 2n bits? n VAX - n normally 8088 - 2n normally

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33 Integer Multiplication: A Consideration n Contrary to addition, the multiplication operation depends on the interpretation: u Consider byte problem: FFh x 02h = ?? u unsigned interp.: 255 x 2 = 510 = 01FEh u signed interpret.: -1 x 2 = -2 = FFFEh n We thus have two different multiplication instructions: u MUL source ;for unsigned multiplication u IMUL source ;for signed multiplication n Where source must be either mem or reg

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34 Multiplication (cont.) n MUL source IMUL source n Notation: Multiplicand x multplier = product n byte source AL x source = AX word source AX x source = DX:AX dword source EAX x source = EDX:EAX n Hence, there is always enough storage to hold the result

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35 Multiplication (cont.) n Nevertheless, CF=OF=1 iff the result cannot be contained within the least significant half (lsh) of its storage location u lsh = AL if source is of type byte u lsh = AX if source is of type word u lsh = EAX if source is of type dword n For MUL: u CF=OF=0 iff the most significant half (msh) is 0 n For IMUL: u CF=OF=0 iff the msh is the sign extension of the lsh

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36 Examples of MUL and IMUL n Say that AX = 1h and BX = FFFFh, then: u InstructionResult DXAXCF/OF mul bx 655350000FFFF 0 imulbx -1FFFFFFFF 0 n Say that AX = FFFFh and BX = FFFFh, then: u InstructionResult DX AX CF/OF mulbx 4294836225 FFFE 0001 1 imulbx 1 0000 0001 0

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37 Examples of MUL and IMUL (cont.) n AL = 30h and BL = 4h, then: u InstructionResultAHALCF/OF mulbl 19200C0 0 imulbl 19200C0 1 n AL = 80h and BL = FFh, then u InstructionResultAHALCF/OF mulbl 326407F80 1 imulbl 1280080 1

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38 Multiplication: An observation n Observe: The differences between the double length products for signed and unsigned multiplication occur in the most significant (left) half. n In machines with single length products, the same instruction can be used with both signed and unsigned multiplication

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39 Additional Multiplication Formats n Question: Originally Intel believed in double length product. What do they think now? n New multiplication instructions IMUL register, immediate (.286) ; register = register * immediate IMUL register1, register2, immediate (.286) ; register1 = register2 * immediate IMUL register1, register2/memory (.386) ; register1 = register1 * register2 ; register1 = register1 * memory n All yield single length products!

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40 Integer Division n Notation for integer division: Ex: 7 2 = 3 r 1 dividend divisor = quotient r remainder n We have 2 instructions for division: u DIV divisor;unsigned division u IDIV divisor;signed division n The divisor must be reg or mem n Convention for IDIV: the remainder has always the same sign as the dividend. Ex: -5 2 = -2 r -1 (not -3 r 1)

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41 Division (cont.) n The divisor determines what will hold the dividend, the quotient, and the remainder: u DivisorDividendQuotientRemainder byteAXALAH wordDX:AXAXDX dwordEDX:EAXEAXEDX n The effect on the flags is undefined n We have a divide overflow whenever the quotient cannot be contained in its destination (AL if divisor is byte...) u execution then traps into INT 0h which displays a message on screen and returns control to DOS

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42 Examples of DIV and IDIV n DX = 0000h, AX = 0005h, BX = FFFEh: u InstructionQuot.Rem.AXDX divbx 0500000005 idivbx -21FFFE0001 n DX = FFFFh, AX = FFFBh, BX = 0002h: u InstructionQuot.Rem.AXDX divbx Divide Overflow idivbx -2-1FFFEFFFF

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43 Examples of DIV and IDIV (cont.) n AX = 0007, BL = FEh: u InstructionQuot.Rem.ALAH divbl 070007 idivbl -31FD01 n AX = 00FBh, BL = FFh: u InstructionQuot.Rem.ALAH divbl 025100FB idivbl Divide Overflow because 251/(-1) = -251 < -128

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44 Preparing for a division n Recall that: u For a byte divisor: the dividend is in AX u For a word divisor:the dividend is in DX:AX u For a dword divisor:the dividend is in EDX:EAX n If the dividend occupies only its least significant half (lsh) we must prepare its most significant half (msh) for a division u For DIV: the msh must be zero u For IDIV: the msh must be the sign extension of the lsh

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45 Preparing for IDIV n To fill the msh of the dividend with the sign extension of its lsh, we use: u CBW (convert byte to word): fills AH with the sign extension of AL u CWD (convert word to double word): fills DX with the sign extension of AX u CDQ (convert double to quad): fills EDX with the sign extension of EAX n Sign extension (recall): u if AX = 8AC0h, then CWD will set DX to FFFFh u if AX = 7F12h, then CWD will set DX to 0000h

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46 Preparing for DIV or IDIV n If AX and BX contain unsigned numbers, to perform AX / BX, you must do xor dx,dx ;to fill DX with 0 ; faster than mov dx, 0 div bx n If AX and BX contain signed numbers, to perform AX / BX, you must do cwd ; fill DX with sign extension of AX idiv bx n Never assign the msh of the dividend to zero before performing IDIV

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