CCB Modification We have built a small patch board with 40.078Mhz VCXO oscillator that allows to test SP with MS without TTC system or hardware changes (replace oscillator) on CCB board
Testing Software Load 254 patterns (2 frames each) representing 1, 2 or 3 muons into Sector Processor FIFO over VME Load fine phase adjustments for SP and MS clocks Send testing patterns out of SP FIFO at 80Mhz on CCB command Read MS FIFO buffers over VME and compare against expected results Read “winner” FIFO from SP over VME and compare against expected results
GTLP Backplane Signals 1.5V 1.0V 0.5V 0V Typical 25 ns GTLP signal Vref_transmitter = 1.0V GTLP Bit_2 from SP to MS Vref_transmitter_1 (SP) is floating GTLP Bit_29 from SP to MS Vref_transmitter_2 (SP) is floating
Hardware problems discovered Sector Processor Vref pins of GTLP transmitters shouldn’t be floating (were connected to 1.0V) SP doesn’t have GTLP terminators for both “winner” lines (were added) Backplane MS_config_done signal was routed to MPC_reserved line (both are outputs!) on the backplane
Test Results No data errors after 275K test iterations (BER < 2.5x10 -10 ) No winner errors after 275K test iterations (BER < 4x10 -9 ) Have checked the SP on all slots (except 11 and 21). Did not find any issues related to mezzanine FPGA.
Safe Window for Data Latching ~10 ns for 2 winner bits (SP) ~8 ns for 32-bit random patterns (MS) ~6.5 ns for specific 32-bit patterns (1 st frame = f0f0f0f0, 2 nd frame = 0f0f0f0f). The reason is that the mean propagation delays of GTLP transceivers (low-to-high and high-to-low) are changing with number of switching outputs. See Fairchild AN-5002.
Latency (LVTTL-GTLP-LVTTL + backplane) 9 ns MS SP1