1. Séminaire CNES : Les CAN pour les applications spatiales Auto-Test Intégré des CAN Y. Bertrand, F. Azaïs, S. Bernard, M. Comte et M. Renovell 28 mai 2002, Toulouse LIRMM : Laboratoire d’ Informatique, de Robotique et de Microélectronique de Montpellier

2. Yves Bertrand 2/21 Outline FIntroduction FHistogram-based BIST FBIST Implementation FPerformance Evaluation FConclusions

3. Yves Bertrand 3/21 Introduction AnalogDigital Mixed-Signal IC Fault-Oriented Test ATPG DFT BIST Specification-Oriented Test ?

4. Yves Bertrand 4/21 Introduction Ideal ADC LSB = FS/2 n Analog input Ideal Transfert Curve 111 110 101 100 011 010 001 000 Digital output V T1 V T2 V T3 V T4 V T5 V T6 V T7 FS

5. Yves Bertrand 5/21 Introduction ADC Parameters Offset ErrorGain Error 111 110 101 100 011 010 001 000 Analog input Digital output N-Linearity Errors Analog input 111 110 101 100 011 010 001 000 Digital output INL DNL 111 110 101 100 011 010 001 000 Analog input Digital output Ideal Offset Gain

6. Yves Bertrand 6/21 Histogram-based BIST Histogram-based Test Histogram H(i) output code Analog input Time 2A V T3 FS 000 001 010 011 100 101 110 111

7. Yves Bertrand 7/21 ADC Analog Waveform Generator Analog Input ADC Parameters Histogram-based BIST Histogram-based BIST Architecture Digital Output n bits Detector Module Control Unit 2 n Memory Words (Measured Histo.) 2 n Memory Words (Ideal Histo.) DSP or  -Processor Exploitation module

8. Yves Bertrand 8/21 Linear Histogram H ideal H extreme 2 Memory Words for the storage of the Ideal Histogram Histogram-based BIST Sinusoidal Histogram Choice of the Input Waveform Non-Uniform Distribution 2 n Memory Words for the storage of the Ideal Histogram H(i) Uniform Distribution

9. Yves Bertrand 9/21 Histogram-based BIST Parameter Evaluation H ideal H extreme Offset n ideal H2 )1(H)2(H    Code i Code Count H(i) Division by constantAdditionSubtraction Code 1Code 2 n m Codes Division by constantAdditionSubtraction Gain -1  ideal m.H )i(H  N2 N1 INL (i)   i j=1 DNL (j)  DNL (i) ideal H )i(H   H Gain -1  ideal m.H )i(H  N2 N1 Division by constantAdditionSubtraction

10. Yves Bertrand 10/21 Histogram-based BIST Time Decomposition Technique 1 Memory Word for the storage of the Measured Histogram Code 1 Processing Code 2 n Processing Code N1 Processing Code N2 Processing Code 1 Processing 2 n Code 2 n Processing Code 1 Processing Code 2 n Processing...................... Step 1: Step 2: Step 1: Step m: Step 1: Step 2 n : Step 1: Step 2 n :...................... Phase 1: Phase 2: Phase 3: Phase 4: TIME Offset Calculation Gain Calculation DNL Calculation INL Calculation Reusable test resources

11. Yves Bertrand 11/21 ADC Triangle Wave Generator Analog Input ADCParameters Histogram-based BIST Optimized BIST Architecture Digital Output n bits Detector Module Control Unit 2 Memory Words (Ideal Histo.) 1 Memory Word (Measured Histo.) Elementary Operators  -  Exploitation module

12. Yves Bertrand 12/21 BIST Implementation Optimized BIST Architecture Detector Module 2 Memory Words (Ideal Histo.) 1 Memory Word (Measured Histo.) Elementary Operators  -  Exploitation module ADC Output Digital Output n bits Control Unit Exploitation module Control Unit Detector Mod.

13. Yves Bertrand 13/21 BIST Implementation FGeneration of the Reference Code FComparison of this Code with the ADC Output Detector Module Counter Comparator Exploitation module Control Unit Detector Mod.

14. Yves Bertrand 14/21 BIST Implementation Detector Module ADC_Out [i+1] DM_Set DM_Clear Next_Code Control Comparator_Out O1[i+1] O2[i+1] 1-bit block [ i+1] O1[i-2] O2[i-2] ADC_Out [i-1] 1-bit block [ i-1] ADC_Out [i] 1-bit block [ i]  Number of 1-bit blocks = N bits Exploitation module Control Unit Detector Mod.

15. Yves Bertrand 15/21 BIST Implementation Exploitation module Control Unit Detector Mod  Up / Down Counter Adder 1 Memory Word (Measured Histo.) H(i) Counter if code = i then R = R + 1  Subtractor H(2 n )-H(1) if code = 1 then R = R + 1 if code = 2 n then R = R + 1 Up/Down Counter  - Divider 2 Memory Words (Ideal Histo.) 1 m.H Ideal H Ideal = 2 P & m = 2 Z (P+Z)-bit shift

16. Yves Bertrand 16/21 BIST Implementation Exploitation module EM_Clear Ext_Clock c2 c1 S1[i+1] S2[i+1] EM_Out[i+1] [ i+1] 1-bit block EM_Out[i] [ i+1] 1-bit block S1[i-2] S2[i-2] EM_Out[i-1] [ i+1] 1-bit block  Number of blocks = F(  Gain,  DNL ) Exploitation module Control Unit Detector Mod.

17. Yves Bertrand 17/21 BIST Implementation Control Unit Library IEEE; use IEEE.std_logic_1164.all entity Contol_Unit is port(ck,startS,endS,In0: in std_logic; c1,c2,clr_DM : Out std_logic); end Control_Unit architecture ArchControl of Control_Unit is type state is (Ini_Etat, o1,o2,o3,o4,o5,o6,o9); signal nextEtat, presEtat: state; begin control : process (presEtat, startS,endS,In0) begin nextEtat <= presEtat case (presEtat) is... VHDL Synopsys Exploitation module Control Unit Detector Mod. [ i+1]

18. Yves Bertrand 18/21 Performance Evaluation Example of BIST Structure Number of bits : 6 Exploitation H Ideal =2 5 & m=2 4 EM_Out[i] [ i+1] 1-bit block 10 x Exploitation module Control unit VHDL Control Unit ADC_Out [i] 1-bit block [ i] 6 x Detector N bits Detector Mod.  DNL = 0.03 LSB  Gain = 0.05 LSB

19. Yves Bertrand 19/21 Performance Evaluation AMS0.8u Example of BIST Structure Area FLASH6 3.3 mm 2 100MS/sec6 bits BIST0.22 mm 2 Relative area : 7 % < 6 bits 

20. Yves Bertrand 20/21 Performances & Discussion Limitation 6 8 10 12 14 Number of bits TEST TIME 300ms 5s 1mn 15s 20mn 5h 22mn F s =1MHz 30ms 500ms 7.5s 2mn 32mn F s =10MHz 6ms 100ms 1.5s 24s 6mn F s =50MHz 3ms 50ms 750ms 12s 3mn F s =100MHz n Trade-off Time-to-area

21. Yves Bertrand 21/21 Conclusion & Future FHigh Level Structure u Linear Histogram u Simplification of the computations u Time Decomposition FLow Level Implementation u Detector Module = Counter u Exploitation Module = Up/Down Counter u Small Control Unit Integrating Histogram-based Test ?