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XPower for CoolRunner™-II CPLDs

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Presentation on theme: "XPower for CoolRunner™-II CPLDs"— Presentation transcript:

1 XPower for CoolRunner™-II CPLDs
This presentation is intended to understand how XPower works for CoolRunner-II CPLDs. It is intended to show the basic concepts, assumptions, and user requirements to correctly use the tool. This discussion is an aid for the user to more accurately estimate power consumption for these CPLDs. It is not intended to show how the GUI works or the flow of XPower. It is also not intended to show complex designs and how these are used in XPower. A simple example is given to demonstrate the concepts of power calculations within XPower and these concepts can be easily ported to larger designs.

2 Overview Design power considerations
Power consumption basics of CMOS devices Calculating power in CoolRunner-II CPLDs Assumptions for CoolRunner-II CPLDs in XPower CoolRunner-II power model in XPower Rank of power consuming nets in CoolRunner-II CPLDs Activity rates Data entry methods Improving accuracy of CoolRunner-II power estimation Design example This discussion begins with what a designer must consider for power supplies such as types of power supplies and their limitations. Prior to a discussion of XPower, it is necessary to describe the basics of power consumption in a CMOS device since the architecture of CoolRunner CPLDs are of this type. This leads into how power is actually calculated within the CoolRunner CPLDs. It is important to understand the assumptions that were made of the user while designing XPower. The power model, which is described in detail, directly relates to these assumptions. Within the power model, some nets consume more power than others. Users must understand which nets consume more power to obtain more accurate power estimations and to reduce overall power consumption. There are two types of Activity Rates that are discussed which the user must understand fully for better power estimates. Additionally, three methods of activity rate data entry are presented, each of which provide different levels of efficiency and accuracy. Most designers are interested in obtaining accurate power estimates. Methods of data entry are described towards this end. A design example is given along with a demonstration of the software.

3 Objectives Power consumption in CoolRunner-II CPLDs
Assumptions for CoolRunner-II CPLDs in XPower Applying the CoolRunner-II power model to a design The highest power consuming nets in CoolRunner-II CPLDs Types of activity rates Types of Data Entry Methods Improving accuracy of CoolRunner-II power estimation Understanding a simple design example using XPower XAPP360 Concepts that should be learned from this discussion include how power is consumed in CoolRunner-II CPLDs and therefore what assumptions were made while developing the power model. How to apply the power model to CoolRunner-II designs is important to obtain accurate power consumption estimates. During the design flow, it is beneficial to understand which nets consume the most power in order to reduce overall power consumption and obtain the most accurate power estimation. Different types of data entry methods are presented and it is important to understand these to obtain the full benefits of XPower. An introduction to the different macrocell configurations is given describing the methods to improve accuracy. It is vital to understand these configurations and a full list of configurations are described in XAPP360. XAPP360 discusses XPLA3 CPLDs, but the principles apply to CoolRunner-II CPLDs.

4 Power Considerations Power Supply requirements Thermal requirements
Batteries DC/DC converters AC power source Power supply voltage Thermal requirements Package types Enclosed environments Industrial applications CoolRunner-II CPLDs Low Power Low Junction Temperature Very predictable power consumption Fast XAPP360 There are several power considerations involved with developing digital systems. First, there is the power supply requirement which may be of different physical types such as battery powered for hand held devices, DC/DC converters, and AC power supplies. Additionally, there is the target system voltage which will have an immediate affect on power consumption. Generally speaking, lower voltages mean lower power. Second, there are thermal considerations. What type of system will be the end application? Likely this is an enclosed system ranging from low power hand held devices to high power and high heat environments such as those in industrial applications. This dictates the form factor of the device where junction temperature differs. XPower is available to the designer as an aid during the design cycle of the end application. XPower can determine both power consumption and junction temperature based on the user’s design. XPower adjusts these parameters based on system voltage and package type respectively. Designers demanding low power, low heat dissipation, low junction temperature, or high reliability should consider designing with Xilinx CoolRunner-II CPLDs. Since the CoolRunner is a CMOS device, the power consumption is very predictable whereas other CPLDs are not as predictable due to the sense amplifier construction. Because CoolRunner-II CPLDs don’t have sense amplifier product terms doesn’t mean they are slow, in fact, these CPLDs are just as fast as those with sense amps. These slides are derived from a discussion found in XAPP360 “Obtaining Accurate Power Estimation for XPLA3 CPLDs using XPower”.

5 Power in a CMOS Device Total Current is composed of two types of current Static Dynamic Static Current Leakage current in the turned off transistor channel Ideally zero Fixed component of Total Current Dynamic Current Switching of the CMOS gate when in the linear region causing transition (crowbar) current Transition time is very fast Relatively small component Charge/Discharge of capacitive poly gate in subsequent logic element XPower combines transition current with capacitive current in the power model CoolRunner CPLDs are true CMOS devices and therefore follow the characteristics of this technology. CoolRunner CPLDs have very low overall total power due to this architecture. What comprises total power in CMOS devices? Power is simply current multiplied by voltage. There are two components for total current: Static current and Dynamic current. Static current is derived from leakage current. When a transistor pair, e.g. an inverter, is in a particular logic state, one transistor is turned on while the other is turned off. The transistor that is turned off should ideally have zero leakage current since it is essentially a switch in the off position. However, due to a weakly inverted channel which is based on the amount of substrate doping, the transistor will conduct a small amount of current. This is a very small, but fixed component of Total Current. Dynamic current is also based on two components: Transition (crowbar) current and Charge/Discharge current. Transition current is developed during the time that the inverter is between states. This is when both transistors are biased in the linear region effectively creating a short circuit from Vdd to GND. The curve of Vgs vs. Idd shows that when the gate voltage is between Vdd and GND potentials, Idd rises significantly. Fortunately, the transition time is very fast developing a low impulse type of current. Consequently, this is a tiny portion of Dynamic Current where Charge/Discharge current is the dominant factor. Once the transistor pair reaches its final state, the turned on transistor must charge (for the P channel transistor) or discharge (for the N channel transistor) the subsequent transistor pair’s gate and routing to the gate. This charging and discharging is the prominent factor in dynamic current. XPower therefore combines transition current with Charge/Discharge current in the power model for simplicity.

6 Calculating Power for CoolRunner CPLDs
Calculating Dynamic Current is an overwhelmingly tedious task XPower is necessary for this calculation Dynamic Current equation Total Current equation Total Power equation I = C × V × f Dynamic It can be an overwhelmingly tedious task to calculate power consumption for every transistor in the device and sum the results. This is where XPower is a necessary tool for the design process. Software can quickly return a quite accurate value for power consumption freeing the designer from this task. Dynamic Current is calculated by multiplying capacitance with voltage and again with frequency. To yield Amperes, the units must be Farads, Volts, Hertz. Capacitance is the sum of all capacitive loads toggling at the specified frequency. For example, a non inverting buffer would be comprised of several transistors all of which present capacitance as a load to the system. All of these capacitive values are summed to provide an equivalent capacitance in the equation. Since all capacitive elements of the buffer toggle at the same frequency, the equation holds true using a lumped capacitance. Total Current is simply the sum of all the individual dynamic currents and static currents. The equation shown is simply the equation for a line: y=mx+b. The y-intercept, b, is given by static current. In the case of the CoolRunner devices, static current is near 30 μA which is essentially 0 mA. This is why CoolRunner Icc vs. Frequency graphs draw the line through zero. The x variable is, of course, frequency. The slope of the line, m, is dependent on two items: voltage and capacitance. The lower the voltage, the less steep the slope and therefore less current is consumed. The same is true for capacitance. Total Power is Total Current multiplied by system voltage.

7 XPower Assumptions for CoolRunner-II CPLDs
Voltage Within published operating limits Constant (no spikes or dips) User must enter appropriate value Timing and frequency Operation above limits yields inaccurate power calculations Input transition times 1.5 ns Correlated in lab at 1.5 ns Actual transitions slower than 1.5 ns will: Increase actual power consumption Cause XPower data to appear lower than actual Lumped capacitance Logic elements (Product Terms, etc.) Used to create a power model Several assumptions were made which are imposed both on XPower and the user: System voltage must be given to the XPower GUI which is within published operating limits. If the user implies voltages outside of these limits, XPower will not estimate power within reasonable results. It is assumed that actual system voltage is constant meaning that there are no spikes or droops over the operation of the device. Variation in system voltage will affect power consumption. The user must specify timing and frequency within published operating limits. Operation outside of these limits will give power calculations that are incorrect. XPower was developed and correlated in a laboratory environment where input signal transition times were set at 1.5 ns. If the actual system experiences input signal transition times slower than 1.5 ns, the system will see greater power consumption. This will appear to the user that XPower is calculating power consumption too low. It is recommended to implement fast transition times on input signals to reduce power consumption. XPower assumes that logic elements such as product terms, ZIA muxes, sum terms, etc. can be modeled as lumped capacitances as described earlier. This assumption is shown in the CoolRunner-II power model designed for XPower.

8 CoolRunner-II Power Model
Simplified model of the CoolRunner-II architecture Somewhat encrypted net names FB1_PT12 Product Term #12 in Function Block #1 FB1_3_Q Q Flip Flop output of Macrocell #3 in Function Block #1 FB4_12_I Input net of Macrocell #12 in Function Block #4 The Power Model for CoolRunner-II CPLDs is a simplified model of the chip architecture, but is constructed to represent the various lumped capacitances that make up the architecture. It is important to have a good understanding of the CoolRunner-II architecture to effectively use XPower. Net names given in the XPower GUI are slightly encoded. For example, FB1_PT12 simply refers to Product Term #12 which resides in Function Block #1. It is not necessary for the user to understand the details of product term numbers, etc. but it is sometimes handy to know which product terms drive which sum terms or macrocells. This can help the user determine at what frequency a subsequent net should be toggling. Most of the internal arrangement of product terms, etc. are automatically considered by XPower and given appropriate frequencies. What is important is to note the macrocell structure given in the power model to obtain a better power estimate. Two nomenclature examples of nets within the macrocells are: FB1_3_Q which is the Q output of the flip flop contained in macrocell #3 which is located in Function Block #1. FB4_12_I which is the input net of macrocell #12 which resides in function block #4.

9 CoolRunner-II Power Model
Nets adjustable by the user I - Input from I/O Q - Flip flop output FB - Feedback to the AIM PT - Product Term output MC_CLK - Macrocell control inputs OR - Output of OR term Nets NOT adjustable by the user AIM - Interconnect Array AND - Input to the register MC_OE - Output Enable signal RST/PST - Reset/Preset inputs to register Of the nets displayed in the XPower GUI, some are not accessible by the user which are automatically adjusted by the XPower tool. Nets adjustable by the user are: • I - Input nets which are tied to an I/O pin • Q - The net associated with the Q output of the flip-flop • FB - A feedback net to the AIM • PT - The output of a product term MC_CLK - The local clock input to the register • OR - The output of the sum term Nets that are not adjustable by the user are: • AIM - The path through the AIM (Auxiliary Interconnect Matrix) AND - The input to the register. Somewhat of a misnomer, this is not the product term output MC_OE - The local output enable signal to the output buffer. RST/PST - The local reset/preset signal to the register.

10 CoolRunner-II Power Consumption
Nets in order of power consumption External Capacitance - Very High O - High GCK - High - Larger with high density devices FB - Medium - Larger with high density devices AIM - Medium I - Low - Medium for Differential Inputs PT - Low OR - Low AND - Very Low MC_CLK - Very Low RST/PST - Very Low MC_OE - Very Low Q - Very Low Designers interested in reducing overall system power consumption should be knowledgeable about which CoolRunner-II nets consume the most power. Listed are the nets from the CoolRunner-II power model that are sorted in order of most power consumption at the top to the least at the bottom. To reduce power, designers should either avoid using the higher power nets or reduce the frequency of these nets. XPower will show the change in power consumption when frequency is changed on these nets and is a useful tool in “What if?” scenarios. External capacitive loading is, by far, the major power consuming net for the device. It consists of PCB trace capacitance and capacitive loading of external device input pins. It is very important to accurately reflect the external capacitive loading and external frequency in XPower to obtain accurate calculations. Current required to charge and discharge the external capacitive loading will be seen at the power pins of the CPLD thereby increasing the power dissipation of the device. It is therefore important to reduce external loading and frequency to obtain lower power results. Some nets listed will change their magnitude of power consumption based on the macrocell count of the CoolRunner. This is simply due to longer interconnecting trace lengths, transistors, and feature sizes (such as the AIM). For example, the input net, FB,will consume more power with the larger devices since it feeds directly into the AIM. The AIM is larger since there are more inputs with larger devices and therefore contains more transistors. The input buffer that drives the FB net is larger to accommodate driving more inputs to the AIM. Trace lengths are longer since the AIM is further from the input pin. All of these factors adds up the capacitive loading of the input net.

11 Activity Rate Absolute Frequency Toggle Rate
Frequency of a net in units of MHz All nets (except Q) in CoolRunner-II CPLDs are specified with absolute frequency Toggle Rate A percentage of the clock frequency Entered as a percentage value Displayed as MHz based on clock frequency 100% toggle rate yields 1/2 frequency of the clock Q nets in CoolRunner-II CPLDs Based on global clocks only When using product term clocks give data in absolute frequency Great for “What if?” scenarios XPower refers to activity rates via two methods: Absolute frequency and Toggle rate. Absolute frequency is simply the rate in MHz at which a net changes state. All nets within the CoolRunner CPLDs, with the exception of Q nets, are to be given values of absolute frequency. Toggle Rates are given as a percentage of the clock frequency. The value is entered into the GUI as a percentage value. Once the value has been entered, XPower will convert the number to a frequency value in MHz. This is applicable to all Q nets in the CoolRunner-II designs that use global clocks. Macrocells that use product term clocks are not to be specified with toggle rates. They should be specified with absolute frequency. For example, a macrocell yields an output of 10MHz which is half the frequency of the 20MHz global clock. This corresponds to a toggle rate of 100%. If the same macrocell were given a toggle rate of 50%, the output would be one quarter of the clock which corresponds to 5MHz. Toggle rate is easily remembered as the percentage of active clock edges the output changes states. Therefore, 100% toggle rate gives an output that toggles on 100% of the active clock edges. A macrocell that is configured to change states on active high clock edges and has a toggle rate of 100% will change state every rising edge of the clock. Therefore this gives half the clock frequency. Toggle rates are great for the “What if?” scenario. Simply change the absolute frequency of the global clock, and XPower will automatically adjust the absolute frequency of all macrocells associated with that clock.

12 Data Entry Methods Data entry by hand Estimate Activity Rates tool
Most accurate, but most tedious method Requires very detailed knowledge of CoolRunner-II architecture Must specify activity rates for all nets Depending on the design, it may be nearly impossible to determine activity rates for all nets Estimate Activity Rates tool Algorithm estimates absolute frequencies of nets not yet set by the user Does not estimate toggle rates Alleviates the tedium, but is less accurate than data entry by hand Must enter all absolute frequencies for primary I/Os by hand Must enter all toggle rates by hand including buried registers There are three primary methods of data entry for XPower. Data entry by hand, Estimate Activity Rates, and Simulation with ModelSim XE. Data entry by hand is very tedious and requires detailed knowledge of the CoolRunner-II architecture. However, it will provide the most accurate results as long as all nets have had correct frequencies and toggle rates set. Any net missing correct data will give inaccurate results. For some designs, it may be nearly impossible to determine the correct activity rates for all nets. Thus, a tool was developed to assist in the major task of data entry. An algorithm was added to the XPower tool that estimates absolute frequencies of nets. This tool is known as Estimate Activity Rates. For inputs to the algorithm, this tool uses frequencies set by the user during the hand entry method or after loading a VCDf ile, described later. It does not estimate toggle rates, but only absolute frequencies. For the tool to work correctly, the user must enter all primary I/O frequencies, and all register toggle rates including buried registers. This method may not be as accurate as 100% hand entry, but will reduce the chance of incorrect data entry as seen in the other method.

13 Data Entry Methods (cont.)
Simulation with ModelSim XE Easiest method Value Change Dump (VCD) file contains frequency data Simulate for sufficient length of time Currently, only top level nets are contained in VCD file Hand edit remaining primary I/Os and registers including buried registers Use Estimate Activity Rates tool The most easy method for using XPower is by using simulation with ModelSim XE. The simulation is capable of giving a Value Change Dump file which contains the frequencies of nets in the simulation as specified by the user. It is vital to simulate the design for a sufficient amount of time. Nets that toggle infrequently may yield frequencies that are magnitudes of order larger than reality. Such nets may be reset or preset types of signals. In the current version of XPower, only top level nets are useable in the VCD file. All primary I/Os, registers and buried registers that are remaining unset by the VCD file must be edited by hand. Finally, the Estimate Activity Rates tool must be used to set frequencies of all remaining nets.

14 Estimate Activity Rates Tool
Sets absolute frequencies only Automatically set nets O GCK I FB AIM PT AND OR MC_CLK RST/PST MC_OE Nets not automatically set External Capacitance Q The tool available from within XPower called Estimate Activity Rates sets absolute frequencies only. Toggle rates are not set by this tool. The following nets are automatically set by this tool: O, GCK, I, FB, AIM, PT, AND, OR, MC_CLK, RST/PST, MC_OE These nets are not automatically set by the tool: External Capacitance, Q The latter nets must be set by hand in all designs to provide proper power calculations.

15 Improving Accuracy External capacitance loads
Loads connected to the I/O pin Printed circuit board trace capacitance Capacitive load of external devices Current is derived from Vcc and GND pins to charge and discharge this load Large source of power consumption Dramatic effect on power consumption Reduce external loads to reduce power consumption For accurate power estimates Provide accurate capacitance value to XPower Provide accurate absolute frequency of external load To improve accuracy of the tool, it is vital to provide correct information to the tool. Two areas are considered in this discussion: External capacitive loads and macrocell configurations: External capacitive loads consist of the capacitance developed from the PCB trace and from external devices. The current required to charge and discharge this capacitance is developed from the Vcc and GND pins of the device driving the loads. This is only applicable to output and bi-directional pins since input pins are driven by other devices which bear the load. This source of capacitance has a dramatic effect on power consumption since, typically, the external capacitance is very large comparatively. Therefore, to reduce power consumption, consider reducing external capacitive loads. To obtain accurate power estimates, it is crucial to provide accurate capacitance values for external loads as well as precise absolute frequencies of these loads.

16 Improving Accuracy (cont.)
Macrocell configurations Users are not exposed to product term numbers AIM is modeled as a non-inverting buffer Macrocells have many configurations, but are understandable by the user This information is most useful for Data entry by hand method Double checking the Estimate Activity Rates tool Proper activity rate information is necessary in the macrocell Improves accuracy Source of all net activity rates Another area to consider for improving accuracy is within the macrocell and the type of configuration they present to the design. Since users are not given product term numbers as they are arranged in the architecture, it is not necessary to discuss product terms. Nor is it useful to discuss the AIM since it is merely modeled as a non-inverting buffer. Macrocells have many possible configurations which are readily understandable by the user. Since there are many configurations, it is important to provide the proper activity rates for macrocell nets within XPower. The macrocell is the source of all nets within the CPLD and therefore it is vital to provide accurate activity rate information so that it is propagated correctly throughout the die to dependant nets.

17 Registered Output Macrocell
Set activity rates of these nets I - Input signal Absolute Frequency GCK - Global Clock Q - Register output Toggle Rate Remaining nets automatically set by XPower using Estimate Activity Rates In this simple example, a macrocell is configured as a registered output which illustrates the toggle rate concept. It should be relatively easy to determine what the absolute frequency of a registered output should be and the absolute frequency of the clock network driving that register. It must be determined what is the percentage rate the output toggles relative to the active edges of the clock. For active high edges, for example, simply divide the output frequency by the clock frequency, then multiply by Take for example a register with an output frequency of 10MHz and a clock at 20MHz. Dividing 10MHz by 20 MHz yields Then multiplying by 200 gives the toggle rate of 100% representing the output changing states on every active edge of the clock. Using this method, it is necessary to set the toggle rate of the register’s Q output. Additionally, it is necessary to set the correct absolute frequency of the I/O pins and global clocks. These things enable XPower to correctly and automatically set the frequencies of the remaining nets in the design based on these initial settings. Further examples, as applied to XPLA3 CPLDs are found in XAPP360 at

18 Summary XPower is a necessity for Simulation with ModelSim XE
Low power designs Designs with a thermal budget Battery operated designs Simulation with ModelSim XE Easiest method Reduces the chance of data entry error Provides accurate activity rate information Requires user to modify fewer nets in XPower CoolRunner-II CPLDs Lowest power 1.8V CPLD in the industry Excellent for handheld, battery powered designs XPower makes it easier to see power savings using the your own designs XPower support for CoolRunner-II will be available in ISE 6.1i XPower is becoming a necessity for designers concerned with power budgets and thermal limits. These types of designers are typically those with hand held applications since these are usually battery powered and have compact form factors. Several design entry methods were discussed with focus on the hand entry method. Not all designs will need the tedious scrutiny of this method, and therefore it is recommended that simulation using ModelSim XE be performed. The discussion regarding the nets of the macrocell was intended to be used to fine tune the data and obtain the highest degree of accuracy. Simulation is by far the easiest data entry method which, by its nature, will reduce the chance of data entry error. Simulation will cover most nets in the design, but some will need adjustment by hand. CoolRunner CPLDs are the lowest power CPLDs in the industry. Because of this feature, they are used in many hand held, battery powered designs. Designers will need this tool to obtain a better understanding of power consumption and thermal dissipation for these types of designs since they are constrained by these properties. XPower makes it easy for the designer to analyze their design quickly.

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