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Hartmut Sadrozinski US-ATLAS 9/22/03 Detector Technologies for an All-Semiconductor Tracker at the sLHC Hartmut F.W. Sadrozinski SCIPP, UC Santa Cruz.

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Presentation on theme: "Hartmut Sadrozinski US-ATLAS 9/22/03 Detector Technologies for an All-Semiconductor Tracker at the sLHC Hartmut F.W. Sadrozinski SCIPP, UC Santa Cruz."— Presentation transcript:

1 Hartmut Sadrozinski US-ATLAS 9/22/03 Detector Technologies for an All-Semiconductor Tracker at the sLHC Hartmut F.W. Sadrozinski SCIPP, UC Santa Cruz

2 Hartmut Sadrozinski US-ATLAS 9/22/03 Divide the sLHC Tracker into 3 radial regions with 10x fluence increase Fluence is a factor 10 higher than at the same radius in LHC: “ move systems outward” SCT -> Straw tubes, Pixels -> SCT, need new Pixels System performance can then be estimated. Guess at a specification of the charge needed in the 3 regions: Radius [cm] Fluence [cm -2 ] Specification for Collected Signal / (CCE) Detector Technology Large areas -> Simple & Inexpensive > ke - (~100%) “present” LHC SCT Technology, Consider: n-on-p ke - (~50%) “present” LHC Pixel Technology ? Consider: n-on-p < ke - (~20%) RD50 - RD39 - RD42 Technology

3 Hartmut Sadrozinski US-ATLAS 9/22/03 Radius / Fluence Limitation due to: Simulations Needed > 50 cm Leakage CurrentTracking Simulations: Layout Optimization 20 – 50 cm Depletion Voltage Tracking Simulations: Strip length and stereo angle Optimization < 20 cm Trapping TimeCharge Collection/Trapping Simulations Required Studies Tracking detector technologies are limited by radiation The limiting process is different in the different radial regions This motivates different studies

4 Hartmut Sadrozinski US-ATLAS 9/22/03 Simple SSD layout at Radius > 20 cm 3 cm strip length vs. 12 for SCT R > 50 cm: Single layers,  z  1cm 20 < R < 50 cm: Back-to-back single-sided  z  1mm Problem: Confusion of stereo assignment Mitigated by length reduction But strips are much easier to build Explore availability of p-type substrates No type inversion Collect electrons Partial depletion operation Potential for semi-3D?

5 Hartmut Sadrozinski US-ATLAS 9/22/03 SSD technology for radius > 20 cm: Recent results from ATLAS SCT beam test illustrates problem with charge collection after type inversion in common p-on-n detectors. N-on-p would provide much more “head room” in bias voltage (cheaper than n-in-n ?) But: electrons have larger Lorenz angle (tilt of SSD)

6 Hartmut Sadrozinski US-ATLAS 9/22/03 Technologies for Inner-most “Pixels” System Limitation: Trapping 1. Charge Trapping in Si SSD: Collected Charge Q = Q o *  (depletion)*  (trapping)  (depletion) depends on V bias, V dep -> effective detector thickness w  (trapping) = exp(-  c /  t ),  c : Collection time  t : Trapping time Trapping time is reduced with radiation damage: 1/  t = 5*(    ns -1 (same for electrons and holes, measured up to   cm -2   t ~ 1/   t = 0.2ns for   cm -2

7 Hartmut Sadrozinski US-ATLAS 9/22/03 2. Charge Collection in Si SSD of thickness w: Assume linear field (Diode case), field at depth x E(x) = Eo + Em*(x/w) = Eo + 2*V dep *(x/w 2 ) Collection time without Saturation  c = ∫dx/v = ∫dx/(  E(x)) = w 2 /(2  V dep )*ln{(1+R)/(R+(x/w))} R determines the over-depletion R = ½*(V bias – V dep )/V dep V dep is approximately proportional to fluence  : V dep (300um)  300V*(    V dep (100um)  30V*(     c = 1/  t ~ 1/   Without saturation  c /  t independent of fluence !

8 Hartmut Sadrozinski US-ATLAS 9/22/03 3. Charge Collection in Si including Saturation: Drift velocity saturates at v  10 7 cm/sec for E > 5*10 4 V/cm for electrons, v about 30% -50% lower for holes Thus the collection time  c depends on the thickness of the depleted region  c = w/v = (w/100um) ns, for heavily damaged detectors (large V dep and E)  c  1 ns for w = 100um Saturation of the drift velocity -->  c /  t ~   c /  t = 1 for 20 um after   cm -2 !

9 Hartmut Sadrozinski US-ATLAS 9/22/03 4. Charge Collection in Si including Saturation: (Simple spread sheet study, agrees with data, full simulations and V. Eremin) Fluence  [cm -2 ] 600V [um]  c /  t Q estimated [k e - ] Q measured [k e - ]   3003/ % 82% Casse et al   3003/ % 65% Casse et al   / %  full simulations Also V. Eremin   50 at 100V0.5/ % 3-D detectors

10 Hartmut Sadrozinski US-ATLAS 9/22/03 3-d Detectors Differ from conventional planar technology, p + and n + electrodes are diffused in small holes along the detector thickness (“3-d” processing) Depletion develops laterally (can be 20 to 100  m): not sensitive to thickness Depletion Sherwood Parker et al., Edge-less detectors n n p p n n n n  m Depletion / Collection de-coupled from Generation: Depletion and Drift over short distance: much higher radiation tolerance

11 Hartmut Sadrozinski US-ATLAS 9/22/03 5. Detector Materials for Pixels for R < 20 cm MaterialCollected SignalComment SiRT< 2 ke - Trapping: Not enough signal SiCryo “Better than RT” e.g. ~ 4 ke - with 3x less traps (?) Can traps kept frozen out permanently ? Cryo Engineering Si3-D ~ 7 ke - Cost of Manufacturing SiCEpi< 2 ke - Trapping still problem, relatively slow collection Cost of wafers DiamondPoly< 3 ke - ?Trapping ? Cost of wafers DiamondSingle“Same as Poly?”Trapping ? Cost of wafers

12 Hartmut Sadrozinski US-ATLAS 9/22/03 R&D Topics: P-type substrates: work with Japanese groups/HPK Find radiation source to irradiate to  = cm -2 Measure trapping on cryogenic detectors Fabricate 3-D detectors with Japanese groups/HPK


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