Presentation on theme: "Next in line… Advance techniques in design optimisations. Introduction to synthesis tools. Design flow using FPGA and ASIC. Summary."— Presentation transcript:
Next in line… Advance techniques in design optimisations. Introduction to synthesis tools. Design flow using FPGA and ASIC. Summary.
Optimisation while building a counter Comparator is checking 2 variables, value[3:0] and q[3:0]. process begin wait until clk’event and clk=’1’ ; some_value if (count = some_value) then count <= 0 ; else count <= count + 1 ; end if ; end process ;
Optimisation of counter: Slightly different syntax (identical functionality): process begin wait until clk’event and clk=’1’ ; if (count = 0) then count <= some_value ; else count <= count - 1 count <= count - 1 ; end if ; end process ; Comparator is checking 1 variable and 1 constant, therefore much smaller. Now we count to zero
Advanced: Think in hardware process (data1, data2) variable x, y, z : unsigned (64 downto 0); begin x := '0' & unsigned(data1); y := '0' & unsigned(data2); z := y - x; if (z(64) = '0') then LE <= '1'; else LE <= '0'; end if; end process; begin LE <= '1' when (data1 <= data2) else '0'; end EG ; Turns out that… 1 is better than 2 using ASIC library from vendor A; 2 is better than 1 (10 times smaller) using ASIC library from vendor B; 1 is the almost the same as 2 using FPGA library from vendor C!
Advanced: Think in hardware Destination architecture Standard cells available “Fit” with synthesizers How good the library designer is
Leonardo Spectrum Leonardo and Spectrum is two parts. –Spectrum is the synthesis engine, text and TCL scripts driven. source compatible –Spectrum is source compatible with AutologicII. –Leonardo is the graphical front end. Level 3 handles ASIC synthesis.
FPGA Express For FPGA! Used in Xilinx Foundation as their default synthesizer. Integrated into Foundation, so handled by Project Manager. Altera just switched to Leonardo Spectrum. ASIC synthesis: Physical Compiler
Can I see my design placed inside FPGA in some way? library IEEE; use IEEE.std_logic_1164.all; entity counter is port ( clk : in std_logic ; value1 : in integer range 0 to 255; count : out integer range 0 to 255); end counter ; architecture EG of counter is signal counting : integer range 0 to 255; begin process begin count <= counting; wait until clk'event and clk='1'; if (counting = 0) then counting <= value1 ; else counting <= counting - 1 ; end if ; end process ; end EG ; Completing Design Flow in FPGA
Your design is here
Advantages in Synthesis to PLDs and FPGAs Flexibility Portability Fast design cycle Some abstractions No need for verifications
Disadvantages in Synthesis Strict coding style for efficient implementation Buried timing Less efficient use to silicon area Only half way to solution No easy verifications
Other Approaches Pre-synthesis analysis Post-synthesis analysis Syntax parsers Templates Formal descriptions Behavioural descriptions System descriptions
Conclusions Basic HDL structures for fundamental digital system components. Synthesize for low power, small area. Automatic synthesis tools cannot replace clever syntax & analysis from designers. Good tools + good designer = good implementation Tools will get clever, but nowhere as good as us.