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8.1 8 Memory Subsystem 1. Classification 2. Architectures 3. Circuits 1) SRAM 2) DRAM 3) Address decoders 4) Sense Amplifier Contents 4. PLA 5. Gate Matrix.

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Presentation on theme: "8.1 8 Memory Subsystem 1. Classification 2. Architectures 3. Circuits 1) SRAM 2) DRAM 3) Address decoders 4) Sense Amplifier Contents 4. PLA 5. Gate Matrix."— Presentation transcript:

1 8.1 8 Memory Subsystem 1. Classification 2. Architectures 3. Circuits 1) SRAM 2) DRAM 3) Address decoders 4) Sense Amplifier Contents 4. PLA 5. Gate Matrix 6. ROM

2 8.2 1. Classification qRWM(Read-Write Memory) l Random Access : SRAM, DRAM l Sequential Access : FIFO, Stack(LIFO) l Content Access : CAM(Associative Memory) qNVRWM(Nonvolatile RWM) l EPROM l E 2 PROM l FLASH qROM l Mask Programmed l OTP(One-Time Programmable) ; PROM

3 8.3 2. Architectures q1-dimensional memory : N(words)  M(bits/word) l Decoder reduces the number of wires

4 8.4 q2-dimensional array structure uses column decoder to make the chip square.

5 8.5 qHierarchical memory architecture using block address l Block address is used to activate only one block. Other blocks(nonactive) are put in power-saving mode.

6 8.6 qArchitecture of large memory

7 8.7 qBasic organization for a 4K SRAM(1989 Philips research).

8 8.8 qSchematic circuit diagram of 64K SRAM(Hitachi 1982).

9 8.9 qAnother schematic of SRAM(column grouping). SRAM chip block diagram

10 8.10 qDesign Considerations l bit line precharge, sense amp enable 등을 위한 모든 clock 의 발생은 address, CS, WE 등 신호의 transition 을 detect 하는 회로에 의해 internal clock 발생기가 trigger 됨으로써 이루어진다.( 전력소모 억제 ) l 2-stage row address decoding : WL driver decodes A1. l Sense amp 는 column switch 앞에, 혹은 뒤에 놓을 수 있다. 앞에 놓을 경우 : column 의 cell pitch 에 맞추기 위해 아주 simple 한 SA 를 사용 뒤에 놓을 경우 : 상대적으로 복잡한 SA 사용가능 (SA 의 input cap. 는 증가 R 윗 그림은 column 을 (1024 column 의 경우, by 4 인 경우 ) 크게 4 로 나누고, 각각 을 16 으로 나누어 각 소 group 의 16 개의 column 을 한 SA 가 담당토록하는 compromise 임.

11 8.11 3. Circuits qAddress decoders l Single stage(10-to-1024) decoder i) # of transistors = 20/NAND 10  1024 = 20,480 ii) Large fanout requirement on buffers generating Xi’s. iii) series-connected transistors limit discharge time.

12 8.12 qPredecoded scheme i) Group 2 bits and predecode the word using 2-bit segments ; (X 9, X 8 ), (X 7, X 6 ), …. (X 1, X 0 ) ii) 2nd-stage decoder logic # of transistors ; 10/NAND 5  1024 +   12,000

13 8.13 qDivided Word Line architecture Global word line selects a block, while the local line is used to activate a word line within the selected block.

14 8.14 qHierarchical word decoding logic

15 8.15 qRow decoder circuits (Complementary AND, pseudo NMOS, cascade NAND)

16 8.16 qTypical Symbolic Layout Style of row decoders

17 8.17 qVarious other decoder circuits(Power saving, Decoder-powered)

18 8.18 qTree style column decoder

19 8.19 qSense Amplifier for SRAM qSingle differential stage 의 전압이득 A v = g m ·r o g m : current/voltage(transducer gain) of M 1, M 2 r o : output impedance( = r o M 1 r o M 2 ) qAv 가 크기 위해서는 M 1 과 P 1 (M 2 와 P 2 ) 가 모두 saturation 영역에 있어야 함. ( Sat. 영역에서 g m = 가 크고, r o 도 크기때문 ) q 따라서 point X 의 전압을 로 precharge 해 두는 것이 response time 을 짧게 하고, signal swing 을 크게하는데 유리. 

20 8.20 qSingle-ended amp 를 두개 symmetric 하게 연결함으로써 voltage gain 을 높인다. ( 다음 단에 latch 나 another double-ended amp. Stage 혹 은 diff. Input 을 갖는 output buffer 를 달면 된다.)

21 8.21 qSRAM sense amp precharged to qSA 의 출력점을 로 충전하여 SA 의 high-gain 영역에서 동작토록 하는 회로. 1 : V 1 은 V DD 로 prech 됨 power-down 상태 2 : WL 이 access 되면 V 1 을 로 prech. 3 : BL, BL 에 전압차가 생기면 high-gain SA 동작하면서 column decoder/switch 인 pass gate 가 동작 data output bus 로 신호전달 4 : power-down 상태

22 8.22 q2 차구간에서 Static 전력소모가 있음

23 8.23 qSRAM circuit before sense Amp.

24 8.24 qEvolution of SRAM cells i) 6- and 4-transistor SRAM cells

25 8.25 ii) Dual-port/double-ended access and dual-port/single access

26 8.26 iii) Content-addressable memory cell

27 8.27 qEvolution of DRAM cells (a) basic bi-stable f/f w/o load(b) 2C-2D(C:control lines, D:data lines)

28 8.28 ( c) 1C-2D (d) 2C-1D scheme

29 8.29 (e) 1C-1D(f) 1C-1D(industry standard DRAM)

30 8.30 qDRAM read cycle

31 8.31

32 8.32

33 8.33 qDummy word line scheme

34 8.34

35 8.35 qDRAM differential sense amp with dummy cell structure

36 8.36 qCross-coupled Latch Assume node 1 & 2 are precharged, and node 2 begins to drop. When clk is on, node 3 pulls down. N2 strongly turns on, leaving n1 off. 주의 ) cross-coupled TR pair 의 layout 이 대칭이어야 함. threshold 전압차이에 의한 영향

37 8.37 qCharge transfer-based Circuit

38 8.38 qCharge-transfer Circuit(cont’d) qOperation Sequence  As clk goes high, node 1 & 2 are precharged; V 1 (V ref -V th, n2 ), V 2 min(V DD, V clk -V th, n3 ) > V ref  n3 turns off.  Cell(n 1, C c ) is selected(Assume V c was ‘0’) Due to charge sharing between C c & C large, V 1 becomes  n2 is turned on until is transferred from C out.i.e., until V 1 reaches V ref -V th. Voltage drop at node 2 due to charge transfer is  : amplif. factor

39 8.39 qSense amplifier for single - Tr. DRAM cells. dummy cell(C d =C c ), dummy bit line complete Symmetry

40 8.40 qOperation 1. Precharge 전에는 BL, DBL 모두 로 되어 있다.* precharge(n 1, n 2 on) 를 통해 node 1,2 가 pull up 된다. 그리고 n1 과 n2 는 off 된다. 2. C c 와 C d 가 select 되어 charge transfer 에 의해 ( =0 라 하자 ) node 1 의 전압은 node 2 의 전압보다 많이 강하 된다. ( C d 는 로 충전되어 있었기 때문 )* 3. Clk1 이 high 가 되어 n4 는 on, n5 는 off(V 1 은 V ss 로 됨 ) n7 이 다시 conduction 되어 BL 이 V ss 로 방전되어 C c 가 ‘0’ 으로 restore 된다. 4. Sel ‘0’ 로 하여 C c 를 isolate 한 후에 clk2 를 on 하여 BL 과 DBL 을 로 함. 그 후에 seld ‘0’ 하여 C d 에 를 만들고 n3 를 off 시킴. (C c 에 ‘1’ 이 저장되어 있는 경우도 비슷한 방식으로 동작한다.) 

41 8.41 Column SA 와 main SA 를 사용한 SRAM SA 회로 매 column 마다 n 개의 colunm 간에 multiplex

42 8.42 (input 신호 ) (Column SA 가 있는 경우 )

43 8.43 (Column SA 가 없는 경우 )

44 8.44 qResistive-load SRAM cells l Undoped polysilicon as resistors with R   1  /  l Just enough(  10 -12 A) to compensate for leakage current of 10 -15 A l BL & BL precharged to V DD, thus preventing slow charging of BL, BL.

45 8.45 qTFT SRAM cell l Instead of traditional PMOS devices, pull-up transistors realized by PMOS TFT(thin-film transistor) on top of the cell structure. l ON current : 10 -8 A, OFF current : 10- 13 A Complementary CMOS Resistive Load TFT cell Number of transistors 6 6 4 4 4(+2 TFT) Cell size 58.2  m 2 (0.7  m rule) 58.2  m 2 (0.7  m rule) 40.8  m 2 (0.7  m rule) 40.8  m 2 (0.7  m rule) 41.1  m 2 (0.8  m rule) 41.1  m 2 (0.8  m rule) Standby current(per cell) 10 -15 A 10 -12 A 10 -13 A

46 8.46 qBipolar SRAM cells : l Very fast SRAMs are necessary for cache & microcode memory in high- speed computers. l SBD(Schottky Barrier Diode) bipolar SRAM

47 8.47 q3-T DRAM cell : l Resulted by removing the loads to obtain 4-T DRAM cell and further removing redundemt complementary pull down device l Separate Read Word line(RWL) & Write word line(WWL) l Refreshing by writing the inverted BL2 signal onto BL1.

48 8.48 q1-T DRAM cell : : charge transfer ratio

49 8.49 q1-T DRAM cell structure :

50 8.50 qTrench capacitor type & Stacked-capacitor type

51 8.51 qNOR-type address decoder

52 8.52 qNAND-type address decoder

53 8.53 qReducing coupling noise bet. WL&BL : Folded bit line.

54 8.54 qReducing coupling noise bet. BL & neighbor bit lines : Transposed bit line : worst-case variation on each bit line. : signal swing on bit line.

55 8.55 4. PLA(Programmable Logic Array) qGenerally two classes exist for implementing control logic functions. l Multi-level logic through logic optimization on random logic l Regular structure type, i.e., ROM : firmware, mask-programmable PLA : Customized logic to remove unnecessary Product(AND) terms and sum(OR) terms.

56 8.56 qSum of product form, F = a  b+c  d i) NAND-NAND PLA 이러한 2-level Boolean 식은 decoder 를 2 단 연속 붙인것으로 볼 수 있다. a b c d F a b c d AND OR F

57 8.57 i) NOR-NOR PLA l NOR-NOR is faster, but requires larger space (  30% additional) than NAND-NAND. a b c d F

58 8.58 qVarious ways for decoding (NOR 형 decoder)(NAND 형 decoder) NOR : fast NAND : compact : diffusion : polysilicon : metal

59 8.59 qComplementary 형 decoder(CMOS-like) l 저전력 소모 l large area

60 8.60 qMOS ROM vs. MOS PLA

61 8.61 (PLA)(ROM)

62 8.62 qVarious Programmable Logic Devices(PLD’ s ) FSM(Finite State Machine)FPLA(Field-Programmable PLA) : PLA with latched feedback

63 8.63 qPLA(Programmable Array Logic) = FPLA where the OR array is not programmable, AND array is field programmable. qROM : (single)mask programmable PLA:(multiple) mask programmable FPLA:field programmable, bulky PAL:field programmable, less bulky

64 8.64 MGA (Multilevel Gate Array)

65 8.65 Associative Logic Matrix

66 8.66 qPseudo-NMOS PLA

67 8.67 qDynamic NMOS PLA NOR 형 NAND 형 T 1 : product line precharge, input latch in T 2 : sum line precharge T 3 : product line evaluate T 4 : sum line evaluate, output latch out

68 8.68 qDynamic CMOS PlA(2-phase) - I

69 8.69 T 1 : product line precharge, latch input T 2 : product line evaluate, T 2 ’:sum line precharge T 3 : sum line evaluate T 4 : latch output qDummy row 는 모든 TR pair 중의 하나는 항상 ‘ON’ 상태이므로 큰 capacitance, C 가 있는것과 같아 Vx 파형 은 파형이 delay 된 것과 같다. C

70 8.70 qDynamic CMOS PLA - II T 1 : product line precharge, latch input/output(master-slave 방식 ) T 2 : product line evaluate T 3 : AND-OR plane connect, sum line evaluate T 4 : sum line evaluate

71 8.71 qDynamic CMOS PLA - V (NORA type) AND plane : NMOS OR plane : PMOS T1T1 T2T2 T 2 (  =low) : p-line precharge, s-line predischarge latch input T 1 (  =high) : p-line, s-line evaluate, latch output

72 8.72 qDecoded PLA l partition input variables into multiple groups

73 8.73 l row folding : partition inputs into two groups such that one can find an order of rows(product lines) with one input group fed from below while the other input group fed from top. qPLA folding(row & column folding)

74 8.74 qPPL(Programmable Path Logic) merging of AND and OR plane. Do=1 if i.e., ; two-level Boolean eq. OR

75 8.75 qAssociative Logic Array(subset of Storage Logic Array) Ex.

76 8.76 qMGA(Multiple Gate Array, or Multi-level PLA)

77 8.77 qMGA with three associative logic matrices

78 8.78 5. Gate Matrix qUse regularly-spaced polysilicon lines for both gate electrode and interconnect. (a) : NMOS TR 과 채널이 분리됨 (b) : 각 TR 을 polysilicon grid 상에 배치 (c) : series( 혹은 parallel) 로 연결된 TR group 을 한 row 에 배치하고 연결.

79 8.79 qRule 1. Polysilicon 은 일정간격으로 수직방향으로 달린다. 2. 인접한 column 같은 row 에 위치한 TR 의 series 연결은 diffusion butting 으로 한다. 3. Metal 은 parallel 연결, 인접되지 않은 TR 의 series 연결 및 각 gate 간 의 연결을 하며, 수평 및 수직방향으로 달린다. 4. Transistor 는 polysilicon column 상에서만 존재한다. 5. Diffusion wire 는 polysilicon grid 중간으로 수직방향으로 ( 짧게 ) 달 릴 수 있다.

80 8.80 qStatic CMOS layout in Gate Matrix  L(f,h) is realizable if h is realizable.  h is realizable if every diffusion runs(vertical) it generates is legal.

81 8.81 qAutomation of Gate Matrix Layout : Ref. O.Wing et.al. “Gate Matrix Layout”, IEEE Trans. on CAD, Vol.4, July. 1985 Find a function f(gate assignment) : assign the transistor gate and output terminal to each column(TR gates connected to the same node must be assigned same column) Find function(net assignment) : assign the net(segment of horiz. Metal line) to each row. Find layout L(f,h) which is realizable* & has min. rows.

82 8.82 qProblem Formulation for Gate Matrix Optimization

83 8.83 qExample : CMOS Half-Adder Circuit

84 8.84 Gate Nets 1N1, N2 2N1, N3 3N4 4N2, N4 5N1, N2, N3, N5 6N3, N4 7N5 Net Representation(Case I) Net Representation(Case II) Problem Statement ; Given a set of nets which connect at gates, find a permutation of gates and an assignment of nets to tracks, such that the number of tracks is minimized. Problem Statement ; Given a set of nets which connect at gates, find a permutation of gates and an assignment of nets to tracks, such that the number of tracks is minimized.

85 8.85 6. ROM(Read Only Memory) qROM cells l Diode cell : consumes large power from WL l Transistor(BJT) cell : consumes less current(I B vs. I C ) l MOSFET cell :

86 8.86 qSharing supply voltage lines and mirroring cells

87 8.87 qNOR ROM with contact programming

88 8.88 qNOR ROM with V th -raising implant or thick-oxide implants.

89 8.89 qNAND Rom

90 8.90 논문을 쓰려면 두 가지 중의 하나를 고르라. 현재 매우 실용적이거나, 당신의 시기에 파급효과가 큰 기술 분야를 고르든지, 아니면 매우 학문적, 이론적인 탁월성을 추구하라. 논문을 쓰려면 두 가지 중의 하나를 고르라. 현재 매우 실용적이거나, 당신의 시기에 파급효과가 큰 기술 분야를 고르든지, 아니면 매우 학문적, 이론적인 탁월성을 추구하라. 논문을 쓰기 전에 논문을 쓰기 전에

91 8.91 힘든 일을 시작하라. 그러면 심각해 질 것이다. 물러서지만 않으면 성공할 것이다. 힘든 일을 시작하라. 그러면 심각해 질 것이다. 물러서지만 않으면 성공할 것이다. 성공의 비결


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