Presentation on theme: "CMP Modeling and DFM AMC-2008 Invited Talk September 23, 2008"— Presentation transcript:
firstname.lastname@example.org http://vlsicad.ucsd.edu CMP Modeling and DFMAMC-2008 Invited TalkSeptember 23, 2008Andrew B. Kahng, UCSDKambiz Samadi, UCSDRasit O. Topaloglu, AMD
2CMP ProcessPost-CMP wafer topography depends on metal density, individual feature widths and spacingsLong-range and short-range phenomenaDesign manuals specify acceptable metal density ranges“Dummy” fills inserted to make layout density more uniformElse, CMP-related problems…Step heightDishingErosionPuddlingOver-removalslurryContains abrasives and chemicalsconditionerA disk with diamond pyramidsImproves removal ratepadwafer
3BEOL Contribution to Variation (IBM) ParameterDelay ImpactBEOL metal(Metal mistrack, thin/thick wires)-10% → +25%Environmental(Voltage islands, IR drop, temperature)15 %Device fatigue (NBTI, hot electron effects)10%Vt and Tox device family tracking(Can have multiple Vt and Tox device families) 5%Model/hardware uncertainty(Per cell type)N/P mistrack(Fast rise/slow fall, fast fall/slow rise)PLL(Jitter, duty cycle, phase error)
4Agenda CMP fill, DFM, and design-awareness Example questionsOpportunities for design-driven fillWhat is still left on the tableRecap
5CMP and Design for Manufacturability Design Timingand PowerR,C ParasiticsTopographyLithographicManufacturabilityDepth of FocusCMPCMP and Fill effectsCu erosion and dishing change resistanceFill helps planarity but changes capacitanceTopographic variation translates to focus variation for imaging of subsequent layers process window linewidth variation R, C variationCMP impacts both IC parametrics and manufacturability
6The CMP Fill Insertion Problem GivenA gridA fill sizeNumber of fills to be insertedto meet target densityOutputFill configuration that minimizesintra- and inter-layer couplingX% improvementInterconnect Coupling (F)So the main problem is, given a gird, fill size and a number of fills to satisfy a certain density, how do we insert the fills into the grid such that we satisfy the fill insertion guidelines. The output we are targeting is an optimal fill configuration, which would yield minimal intra- and inter-layer coupling.
7Current CMP Fill Insertion Approach Layout density verified in fixed-size “windows”Primitive fill insertion methods – e.g.:Intersect array of potential fill shapes with empty spaceAdjust sizes and spacings, or iteratively execute a ‘multi-pass’ heuristic, to improve density variation and reduce the number of fill shapesHandled by either design house or foundry
8Optimizers Have Improved (1998-present) Global optimization with millions of variables in large linear program – Kahng et al. 1998)Optimization outcome very well-behaved“Difficult” image sensor chip
9Pre-/Post- Fill Densities Original Density Histogram (DD = 31%)minFillDensity Histogram(DD = 15%)minVar Density Histogram(DD = 13%)
10Existing CMP Fill Insertion Approach Layout density checked in fixed-size “windows”Primitive fill insertion methods – e.g.:Intersect array of potential fill shapes with empty spaceAdjust sizes and spacings, or iteratively execute a ‘multi-pass’ heuristic, to improve density variation and reduce the number of fill shapesHandled by either design house or foundryKey issue: fill impact on timing, noise, powerIntralayer coupling: keep-off design rule defines minimum spacing between fill and interconnectLarger keep-off less performance impact, but worse density control, more variation and performance impact…Smaller keep-off better density control and less variation, but more capacitance, performance impact…Conflicting goals !!!Interlayer coupling: no design rulesKey word: “design”
11What Do We Want? Objective for Manufacturability = Minimum Variation subject to upper bound on window densityObjective for Design = Minimum Fillsubject to upper bound on window density variationFor Manufacturability at 65nm and below:Multiple relevant planarization length scales: control density at multiple window sizesN-layer BEOL stack: control density in a multi-layer senseCoupling, etch, OPC etc.: provide “staggered” fill patterns or wire-like (“track”) fillMechanical stability in low-k: achieve (maximal) via fillBetter CMP modeling: achieve smoothness of densityAnalog and mixed-signal variability: symmetric fill…… all within a CMP model-driven framework
12Example of Symmetric Fill (Analog Regions) Analog CellAxis of Symmetry
13Also Want Design-Driven Fill Global optimizationCMP model-driven fill synthesisMust tightly couple CMP model to parasitic extraction and timing analysis enginesEfficiency of design flow is an issue internal CMP model vs. signoff CMP modelDesign-driven fill synthesisDesign concerns: timing, signal integrity, powerConcurrent analysis of fill impact on both topography and timingNew optimizations possibleTrade OPC cost for variability ?Good design practices rewarded by reduced BEOL guardband in design ?Fix hold time violations by inserting extra fill ?“Intelligent” FillInternal CMP ModelLayout, Design Data, Fill ConstraintsPost-Fill Layout, ReportsSignoff CMP ModelUniform Effective Density +Step Height Objective
14Example: Timing-Aware Fill General guidelinesMinimize total number of fill featuresMinimize fill feature sizeMaximize space between fill featuresMaximize buffer distance between original and fill featuresSample observations in literatureMotorola [Grobman et al., 2001]: key parameters are fill feature size and keep-out distanceSamsung [Lee et al., 2003]: floating fills must be included in chip-level RC extraction and timing analysis to avoid timing errorsMIT MTL [Stine et al., 1998]: rule-based area fill methodology to minimize added interconnect coupling capacitanceNot a new concept, but only now reaching production design flows
17Example Questions (Design Flow) Is CMP fill impact on dynamic power (CV2f) large enough to worry about?Can CMP fill meaningfully improve timing robustness ?Shortcut power/ground distribution networks with grounded fill less IR drop ?Use fill to add extra capacitance to hold time critical paths more robust timing ? (And, additional decoupling cap?)What good layout design practices correspond to (can be incented by) reduced RC extraction guardband?How tightly must CMP modeling be integrated into the design flow ?Which tool (placer, router, physical verification, …) owns the CMP-related signoffs of performance and manufacturability ?
18Example Questions (CMP Modeling) What layout parameters must be comprehended by a CMP model?Calibration data for each grid point:X (um), Y (um)DensityCu thickness (A)Dielectric thickness (A)Optional: Pre-CMP Cu thickness, trench depth, barrier thickness, etc.Test LayoutsSignoff CMP Model(or silicon)Layout, Design Data, Fill ConstraintsTopography Predictions(or measurements)Intelligent FillApproximation of Signoff CMP ModelUniform Effective Density +Step Height ObjectiveInternal CMP ModelHow do we achieve a CMP model that is optimizable (fast, simple, accurate, …)?Post-Fill Layout, ReportsSignoff CMP ModelAre CMP processes and models stable enough to drive design flows?
19Example Questions (Manufacturing Closure) Side view showing thickness variation over regions with dense and sparse layout.Top view showing CD variation when a line is patterned over a region with uneven wafer topography, i.e., under conditions of varying defocus.How tightly do we need to connect OPC to post-CMP topography simulation ?What fill patterning strategies offer the best variability – mask cost tradeoff ?
20Agenda CMP fill, DFM, and design-awareness Example questionsOpportunities for design-driven fillWhat is still left on the tableRecap
21Design- (Timing)-Aware Fill keep-off distancePreserves performance while addressing density objectivesShown: avoidance of fill on same/adjacent layers near a critical netTiming-driven place & route creates natural “victims” for fill insertion when it leaves extra space around a critical net !Other issues: OPC, data volume, …
22What We Leave on the Table: An Example More sophisticated pattern synthesis guidelines exist but have not been automatedWant automationWant to account for circuit timing in fill insertionWant to account for interlayer coupling impact on timingWant to gain back the capacitance increase introduced by timing-unaware (traditional) fillsWant power-aware fill for power-critical circuitsNext few slides: an ‘energy model’ heuristic for fill pattern synthesisExample: Place fills to form a hour-glass shapeMinimize number of fills close to interconnectsPlace fills away from interconnects.A physical analogy is present, where fill insertion is analogous to electrons filling energy levels from lower energies to higher in an atom.
23Adaptive Region Definition Region-based instead of window-based fill insertionMaximum-width empty regions identified between facing interconnects, using scanline algorithmAfter stripping out keep-off distances, a grid holding possible fill locations is formedIf orthogonal interconnect segments exist, disable overlapping grid rectangle locationsInterconnectRegionGrid rectangleKeep-off distance
24The Grid Model Utilizing Bonds In this example, there are 36 rectangles with two fills in the grid shown belowAn auxiliary frame is formed holding grid rectangles with bonds in betweenEach bond has an adjustable energyOriginally considered physical analogy of electrons filling orbits…When inserting a fill, bonds incident to a rectangle are summed up to find an energy; we find a minimum energy location to insert a fillBonds incident to a locationRegionGrid rectangleInterconnectKeep-off distanceVertical bondFillAuxiliary frameHorizontal bond
25Energy Modeling in a Grid Modeling of bonds indicates which location should be filled with higher priorityModel is flexible enough to satisfy target guidelinesAdjustable four-parameter model for vertical and horizontal bondsAlthough we use linear models, second-order and more complex models can also be usedZ axis gives the bond energy.Vertical model:YHorizontal model:i : enumeration for a row of grid rectangle locationsj : enumeration for a column of grid rectangle locationsimid : middle row numberjmid : middle column number,,, : fitting parametersXEnergies for vertical bondsEnergies for horizontal bonds
26Experimental Setup and Protocol Cadence SOC Encounter v5.2 used for placement and clock tree synthesis and NanoRoute used for routingSynopsys StarRCXT used for RC extractionC++ code for proposed fill insertion methodology MFO (Metal Fill Optimizer).Comparison against best available industry tools : Mentor Calibre, Blaze IFTSMC 65nm GPlus libraryS38417, AES, ALU and an industrial (microprocessor) testcaseCompare impact of fill algorithm on timing and powerFill Design Rules from Library Exchange FileSizes for Traditional Fill
27Interlayer-Aware Fill Synthesis Flow 1. Place, synthesize clock network and route design2. Extract SPEF parasitics from DEF3. Run static timing analysis using SPEF file from Step 24. Use Perl scripts to obtain top critical net names5. Check critical nets on neighboring layers for each net6. Update energy values for bonds7. Insert interlayer-aware fillsAdd vertical bondsSlack Comparison
28Power-Aware FillAlter flow to handle interconnect switching power criticalityPlace, synthesize clock network and route designExtract SPEF parasitics from DEFCompute interconnect switching power using SPEF file from Step 2Use Perl scripts to obtain top power-critical net namesCheck critical nets on neighboring layers for each netUpdate energy values for bondsInsert power-aware fills
29Timing Slack Results Timing slacks shown Less negative (towards the right) is betterProposed Metal Fill Optimizer (MFO) outperforms intelligent fill (IF) variations
30Post-Fill Topographies and Histograms Core1 of industrial testcaseTraditional fillMFO fillWe obtain a histogram with a single peak
31Agenda CMP fill, DFM, and design-awareness Example questionsOpportunities for design-driven fillWhat is still left on the tableRecap
32Recap: What’s on the Table Example of a physically-motivated, simple heuristicTestbed with 65GP process and fill design rules, leading-edge commercial toolsAutomation of fill insertion guidelines and intuitionsLarge testcases including an industrial (uP) testcaseInterlayer layout awareness utilized for first timeTiming-aware and power-aware fill optionsCan reduce fill impact on timingby up to 85% for 30% pattern densityby up to 65% for 60% pattern densitySignificant value is left on the table by today’s CMP fill methodologiesAlthough it is not possible to improve performance with respect to no fill case, it is possible to reduce the fill impact on timing.
33Recap: Example Open Questions Design FlowIs CMP fill impact on dynamic power (CV2f) large enough to worry about?Can CMP fill meaningfully improve timing robustness ?Can good (layout) design practices correspond to (can be incented by) reduced RC extraction guardband ?How tightly must CMP modeling be integrated into the design flow ?CMP ModelingWhich layout parameters are necessary to feed a CMP model?How do we achieve a CMP model that is optimizable (fast, simple, accurate, …)?Are CMP processes and models stable enough to drive design flows?Manufacturing HandoffHow tightly do we need to connect OPC to post-CMP topography simulation ??What fill patterning strategies offer the best variability – mask cost tradeoff ?Although it is not possible to improve performance with respect to no fill case, it is possible to reduce the fill impact on timing.33
35Religious Questions in BEOL DFM Should CMP fill be owned by the routing / timing closure tool or by the DRC / PG tool?Answer: proper fill is best achieved today post-layout by a tool that maintains the signoffMust fill be “timing-driven”, or is “timing-aware” sufficient?Answer: “Timing-aware” is likely sufficient through the 45nm nodeAre CMP and litho simulations for “more accurate parasitics and signoff” really necessary?Answer: Probably not. CDs and thickness variations are “self-compensating” w.r.t. timing. Guardbands are reasonable. There is a big mess with existing calibrations of the RC extraction tool to silicon.If two solutions both meet the spec, are they of equal value?How elaborate must cost functions and layout knobs be for EDA tools to understand via yield / reliability, EM, etc.?...
36“Intelligent” Fill Goals for 65nm and Beyond True timing- and SI-awarenessDriven by internal engines for incremental extraction, delay calculation, static timing/noise analysisOpen Question: is this done by the router? Or post-layout processing?True multi-layer, multi-window global optimization of effective density smoothness and uniformityRecall: millions of “tiles” – can we optimize all fill on all layers simultaneously?Analog fill, capacitor fill, via fillFloating, grounded and track fillStandalone, ECO, and ripup-refill use modelsSupports thickness bias models (CMP predictors)Key technology for managing BEOL variability and enhancing parametric yieldFABLESS VERSIONSlide Objective – Reinforce the message
37Conclusions: Futures for CMP/Fill in DFM Goal: Design convergenceIntegrate design intent and physical modelsCMP simulation + fill pattern synthesis + RCX + timing/SI drivenPerformance awarenessMaintain timing and SI closure“Multi-use” fill: IR drop management, decap creationDevice layer: STI CMP modeling / fill synthesis, etch dummyTopography awarenessClose the loop back to RCX, fill pattern synthesis, OPC guidanceIntelligent fill pattern synthesisMinimum variation and smoothness in addition to density boundsHandle MANY constraints at once: multi-window, multi-layer, etc.Optional mixing of grounded and floating fillMask data volume control (e.g., shot-size aware, compressible fill)