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Module18 :SoC Platform Prototypes ㈜휴인스 송태훈. 2 Copyright ⓒ 2003 ( 모듈 18) 목차 SoC Platform Prototype 5 Design Step for SoC Prototype Processor-based Prototyping.

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Presentation on theme: "Module18 :SoC Platform Prototypes ㈜휴인스 송태훈. 2 Copyright ⓒ 2003 ( 모듈 18) 목차 SoC Platform Prototype 5 Design Step for SoC Prototype Processor-based Prototyping."— Presentation transcript:

1 Module18 :SoC Platform Prototypes ㈜휴인스 송태훈

2 2 Copyright ⓒ 2003 ( 모듈 18) 목차 SoC Platform Prototype 5 Design Step for SoC Prototype Processor-based Prototyping Development Tools ARM Device Overview Verification Tools Configuration Method

3 3 Copyright ⓒ 2003 Products are needed  To increase performance, reduce costs and enhance features  The use of newer, faster and cheaper technologies  More functions and features to be placed on a single piece of silicon  Integrated in a system-on-chip with new functions added. Peripheral Devices are needed  These include timers, DMA engines, interrupt controllers and memory controllers  In many cost-sensitive applications, a shared memory structure is utilized to reduce memory component costs SoC Platform Prototype

4 4 Copyright ⓒ 2003 Embedded Processor  ARM : ARM922T, ARM926EJ-S, ARM1136  Altera : Excalibur (ARM922T, FPGA)  Motorola : PowerPC  XilinX : Virtex II Pro (IBM405GP, FPGA)  MIPS : MIPS4K Re configurable FPGA  XilinX Virtex II, Spartan  Altera Stratix, Cyclone, APEX, Excalibur Memory Block  SDRAM, DDRRAM  Flash Memory SoC Platform Prototype

5 5 Copyright ⓒ 2003 All the peripheral functions required for a basic SOC  UART, Ethernet 10/100M, 1394, USB2.0  PCI, PC104, PCMCIA, CF+, Cardbus  DMA, Interrupt Request,  TFT LCD, Text LCD, FND  Key PAD, LED, PB Switch IP  MP3, MPEG4, H.264, MJPEG, JPEG, Memory Controller, PCI  USB Controller, UART Controller etc Bus Architecture  AMBA Spec. 2.0 Operating System  Linux, Nucleus RTOS, Vxworks, Qplus SoC Platform Prototype

6 6 Copyright ⓒ 2003 SoC Platform Prototype Example General CPU DSP Actuator Controller PLLs Sensor Controller Display Controller Configure FPGA/ CPLD ADC/DAC Network Interface USB/UART 표준 Interface Network 기능 지원 Analog Interface Reconfigurable H/W S/W 구동 / 통신 기능 지원 RTOS

7 7 Copyright ⓒ 2003 5 Design Step for SoC

8 8 Copyright ⓒ 2003 HW Development SW Development SW Integration HW RTL Model Real Prototype : Validation/Qualification SW Dev. EDA Tools HW Dev. Software Hardware Real HW SW Design HW Design System Specifications Traditional Design Step for SoC

9 9 Copyright ⓒ 2003 Architectural Design Platform Specification SW Generation Virtual Prototype SW Integration HW RTL Model Real Prototype : Verification SW Dev. Architectures EDA Tools Boards HW Dev. Functional Design Ideal Architecture Virtual Architecture System Design Environment Co-Simulation SoftwareHardware Real HW Detailed Co-Simulation System Design System Specifications Design Step for SoC

10 SoC Platform Prototype Processor-based Prototyping

11 11 Copyright ⓒ 2003 SoC Platform Prototype

12 12 Copyright ⓒ 2003 SpecHardware Excalibur ARM922T (1020pin ) FPGA Gates 100 만 게이트 동작 속도 AHB1 : 200MHz, AHB2 : 100MHz 내부 메모리 SRAM : 256K, DPRAM : 128K Flash16MB SDRAM 128MB 기본, 최대 512MB 설치 EPC2 16MB (2M × 8EA) Multi ICE 에뮬레이터 포트 JTAG 파일 다운로드, 디버깅 포트 ETM ARM9 Embedded Trace Macrocell COM Port 통신 포트 2EA Camera Port CMOS Image Sensor SoC Platform - Hardware

13 13 Copyright ⓒ 2003 Spec.Hardware USB Universal Serial Port Ethernet 10/100M bps 이더넷 포트 IDE HDD 인터페이스 40 pin 포트 TFT LCD 3.5 인치 칼라 TFT LCD 7 Segment 1EA Text LCD 2 × 20 Text LCD Keypad 1,2,3,4,5,6,7,8,9,0 Key Expansion Port 100 핀 외부카드, AD/DA Port SoC-LiNUX SoC-LiNUX Ver 2.4.19 IP 및 리눅스 BSP Ethernet, USB, Text LCD, TFT LCD, IDE, 7-Segment, Keypad SoC Platform - Hardware

14 14 Copyright ⓒ 2003 SpecSoftware Linux Kernel Kernel Kernel based on Linux 2.4.19 Power management support JFFS2 Flash Memory File System Bootloader BLOB Device Driver 7-Segment device driver Text LCD device driver TFT LCD device driver LED device driver SDRAM device driver 3.5” Color TFT LCD device driver UART device driver USB device driver 10/100M bps Ethernet device driver SoC Platform - Software

15 15 Copyright ⓒ 2003 Quartus II 설계사양 정의 ( 기능, 타이밍 ) Hardware Software Debugger+ Trace Analyzer Multi ICE, Multi Trace Verilog / VHDL 코딩 ModelSIM ADS Compiler/Linker/ Relocator 하드웨어 소프트웨어 SoC Platform ARM922T+FPGA LiNUX 운영체제 Nucleus OS User Code Libraries SoC-LiNUX Ethernet, TFT LCD, USB, IDE, Camera Interface C Header files Peripheral drivers SoC Platform Design Flow C 코딩

16 16 Copyright ⓒ 2003 5 wire JTAG Trace Debug Tools running on host Data Address Control BREAKPT EmbeddedICE Execution Unit SoC ARM CPU Macrocell ETM Trace Port Multi-ICE MultiTRACE TAP JTAG Port Debugging – Multi-ICE

17 17 Copyright ⓒ 2003 Block Diagram

18 18 Copyright ⓒ 2003 Co-Simulation Hardware/Software Co-Simulation ModelSIM ADS

19 SoC Platform Prototype Development Tools

20 20 Copyright ⓒ 2003 회로 설계및 시뮬레이션, 에뮬레이션 환경 (1) Altera Quartus – EDA Software Tools (2) ARM Developer Suite 1.2 – C Compiler ARMasm(Assembler), Compilers (ARM C/C++ Compiler) ARMlink (ARM linker), AXD – ARM debugger, Adwu – ARM debugger for windows/Unix Fromelf – Format Changer (ELF to other formats) (3) ModelSIM - Simulator (4) ARM Multi ICE - Emulator 리눅스 운영체제 (1)SoC-LiNUX O.S. 2.4.x Kernel (2)SoC-GNU Cross Compiler Tool Kit (3)SoC-LiNUX Bootloader Development Tools

21 21 Copyright ⓒ 2003 S/W Requirements - Quartus

22 22 Copyright ⓒ 2003 S/W Requirements – Verilog HDL, VHDL

23 23 Copyright ⓒ 2003 S/W Requirements - ModelSIM

24 24 Copyright ⓒ 2003 ADS C Compiler

25 SoC Platform Prototype ARM Device Overview

26 26 Copyright ⓒ 2003 ARM922T Features 32 Bit RISC Processor  200MHz ARM922T ™ High Performance.18 µm Process AMBA ™ Bus Architecture  Industry Standard Bus Architecture 내부 Memory  Single Port and Dual Port 외부 Memory  SDRAM, DDRSRAM, FLASH, SRAM

27 27 Copyright ⓒ 2003 ARM922T Processor ARM922 ™ 기반 (ARM920 ™ Derivative) 고속 Cache (8KB Instruction + 8KB Data) SRAM and DPRAM 내장 MMU 기능 (RTOS 지원 ) 200MHz on Altera ®, 0.18u Process 향상된 system Debug 기능 내장 Based on ARM9TDMI core  Five stage pipeline  Harvard bus architecture ARM9 - T- Thumb Architecture Extension D- Core has Debug Extensions M- Core has an enhanced Multiplier I- Core has EmbeddedICE Logic Extension

28 28 Copyright ⓒ 2003 ARM + FPGA 구조 PLL Timer UART Interrupt Controller Watchdog Timer JTAG 256 Kbytes SRAM 128 Kbytes DPRAM Embedded Processor Stripe PLD 100 만 게이트 FPGA Trace Module ARM922T SRAM DPRAM External Memory Interfaces Processor & Interfaces I-CACHED-CACHE ARM 8K Bytes8K Bytes LEs38400 ESB Bytes 40K Excalibur – ARM922T

29 29 Copyright ⓒ 2003 AMBA High Performance Bus (AHB) AMBA - Advanced Micro-controller Bus Architecture Embedded Stripe and PLD Devices 연결 200MHz Maximum Clock Rate 32 Bit Wide Pipelined Bus  Burst transfers - one cycle per data word Multi-master With Distributed Address Decoding  Single-cycle bus master handover Split Transactions Extensions  multi-master bus 에서 bus Bandwith 이용 극대화 가능

30 30 Copyright ⓒ 2003 PLL’s PLL’s Provide Clock Boost Multiplication Only  Default power-up operation is bypass  Program control registers through configuration logic or the embedded processor  State machine control to put PLL in bypass mode if lock is lost  Can change PLL frequency with proper software control PLL1  Clock for processor and peripheral bus  Up to 400 MHz operation divided by 2 or 4 PLL2  Clock for the SDRAM controller  Up to 266 MHz operation

31 31 Copyright ⓒ 2003 Memory Hierarchy Hard Logic PLD AHB 1-2 Bridge SDRAM Controller PLD Application Interfaces Single Port SRAM #1 Processor + MMU + Cache AHB1 AHB2 Memory Mapped Peripherals SDRAM SRAMFlash PLD - AHB2 Bridge PLD Master(s) Bus Expansion Single Port SRAM #2 Arbiter #1Arbiter #2 Dual Port SRAM #1 Dual Port SRAM #2 Depth / Width Muxing PLD Master Bus Clk is application dependent Secondary Bus (AHB2) <= 100MHz Processor Local Bus (AHB1) <= 200MHz AHB2 Arbiter #1Arbiter #2 AHB1

32 32 Copyright ⓒ 2003 SDRAM Controller Stripe 에 SDRAM External Memory controller Runs Asynchronously to AHB1 or AHB2 Byte, Half-word, and Word Transfers 2 Blocks and up to 512 Mbytes PC100/133 SDR SDRAMs SDRAM must be initialized through software control

33 33 Copyright ⓒ 2003 Expansion Bus Interface (EBI) External Memory Mapped Devices 에 인터페이스 기능 제공 Flash Memories or Memory Mapped Peripherals 와 AHB2 Bus Masters 사이에 속도 조절 기능 Four Chip Select Outputs  각 Address Space 는 8- or 16-Bit Mode 로 동작 가능. Split Bus Transactions 지원  다른 AHB2 Bus Masters 의 stalling 방지 Support both synchronous & asynchronous mode

34 34 Copyright ⓒ 2003 UART 5 to 8 data bits 1 or 2 stop bits Even, odd, stick, or no parity 75 to 230,400 baud rate 16-byte transmit FIFO 16-byte receive FIFO. Programmable baud generator Internal diagnostic capabilities Modem communication support

35 35 Copyright ⓒ 2003 Interrupt Interrupt Controller ARM 922T

36 Verification Tools

37 37 Copyright ⓒ 2003 Bus Functional Model Verifies the ability of PLD Peripherals to AHB Protocol  AMBA AHB Masters and Slaves Models AHB Transactions  Includes Master Port and Slave Port Bus Transactors  Models AHB Master and AHB Slave - Accepts and Transmits AHB Protocol Signals

38 38 Copyright ⓒ 2003 Embedded Stripe Model Verification ROM Model SDRAM Model Excalibur Stripe PLD Logic Stripe-to-PLD (Master Port) EBI Port SDRAM Port Master Slave PLD-to-Stripe (Slave Port) Bus Functional Model Verification Full Stripe Model Verification

39 39 Copyright ⓒ 2003 Stripe Model Processor Timer Interrupt Controller UART EBI DPRAM, SRAM SDRAM Controller AHB1-2 Bridge Stripe-to-PLD Bridge PLD-to-Stripe Bridge PLLs (limited model of behavior) PLD Configuration Not Modeled Watchdog Timer PLL AHB 1-2 Bridge Dual Port SRAM SDRAM Controller Single Port SRAM 32 bit RISC Processor Interrupt Controller AHB1 AHB2 APEX 20KE PLD - Stripe Bridge PLD Master Configuration Logic Master Reset Module Timer PLD Slave UART Bus Expansion (EBI) Stripe - PLD Bridge PLD Slave PLD Module PLD Module

40 40 Copyright ⓒ 2003 Full Stripe Model Verification Tool Flow Netlist Output Quartus II Gate-Level / Timing Excalibur MegaWizard Configured Stripe Instance Top Level Design User Selections PLD Logic 3 rd Party Synthesis Test bench ROM model SDRAM Model C / Assembly Code ModelSim/ VCS Behavioral RTL BFM

41 41 Copyright ⓒ 2003 EBI Signals AHB Signals ALU Outputs Registers Simulation Results

42 Configuration Methods

43 43 Copyright ⓒ 2003 Configuration Methods Processor Centric  Boot From Flash PLD Centric  Passive Serial  Passive Parallel  JTAG

44 44 Copyright ⓒ 2003 Configuration File in Flash The intel.HEX programming file is generated by a combined effort of Q uartus II and external softwares  The.HEX component is made by Quartus II in Software Mode or by externa l software tool  The.SBI component is made by Quartus II in Hardware mode  The.SBD component is made by the Excalibur MegaWizard 8-bit/16-bit FLASH EBI Excalibur ARM Processor Quartus II User H/W Design Other IP Quartus II OR Industry Standard Compiler/Linker/ Relocator User S/WDesign Libraries RTOS intel.HEX.HEX.SBI = +.SBD +

45 45 Copyright ⓒ 2003 Configuration Files in PLD -centric Mode Serial / Parallel PLD Configurator Dowload Cable Excalibur ARM Processor Config Port OR Quartus II User H/W Design Other IP Quartus II OR Industry Standard Compiler/Linker/ Relocator User S/WDesign Libraries RTOS.SOF.POF/.RBF/.TTF/.HEXOUT.SOF.POF/.RBF/.TTF/.HEXOUT.HEX.PSOF = +.SBD +

46 46 Copyright ⓒ 2003 ( 모듈 18) 참고문헌

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