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USBpix Upgrade V. Filimonov, T. Hemperek, F. Hügging, H. Krüger, N. Wermes ATLAB ANNUAL ASSEMBLY 18 th February 2013.

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Presentation on theme: "USBpix Upgrade V. Filimonov, T. Hemperek, F. Hügging, H. Krüger, N. Wermes ATLAB ANNUAL ASSEMBLY 18 th February 2013."— Presentation transcript:

1 USBpix Upgrade V. Filimonov, T. Hemperek, F. Hügging, H. Krüger, N. Wermes ATLAB ANNUAL ASSEMBLY 18 th February 2013

2 Outline 2 18 February '13 USBpix Upgrade Research project overview Migrating from FX2 to FX3 Firmware development

3 Research project overview 3 Pixel detector electronics for ATLAS Upgrade Readout ASICs (FE-I4) Test environment (USBpix) 18 February '13 USBpix Upgrade HL-LHC outer layers stave concept: m long stave chip-modules per stave 16 on the top, 16 on the bottom

4 Research project overview 4 USBpix Test System (Test system hardware) 18 February '13 USBpix Upgrade USBpix system for FE-I4 single chip read-out

5 Research project overview 5 Upgrade Plans for USBpix 18 February '13 USBpix Upgrade Resources on the MultiIO board are coming to their limits 2 MB SRAM FPGA resources (Spartan 3, XC3S1000) Data bandwidth (USB 2.0, ~15 Mbyte/s) → Simultaneous r/o of four chips and support of new chip generations with higher data rates becomes challenging Requirements: – Downward compatible to USBpix adapter cards and SW KEL connector USB interface for low-level software compatibility – larger FPGA and memory – USB 2.0 → USB 3.0 – Possible data bandwidth (~ 150 Mbyte/s)

6 Research project overview 6 Upgrade Plans for USBpix 18 February '13 USBpix Upgrade Commercial board (Linera FMU3-S6 Series FPGA Module) Custom made carrier PCB FMU3-S6 series FPGA module 65mm x 50mm board size USB3 Connectivity, including software drivers and APIs Xilinx Spartan6 LX45 application FPGA (Available also with LX150) 1Gbit DDR3 SDRAM (Optional 2 or 4 Gbit) MicroSD card slot, accessible from FPGA Very easy to integrate: Single 5V supply Programmable via USB3.0 port, JTAG or the on-board flash pin high speed board-to-board connectors to mount on a host-board 150 user I/O signals. 72 differential pairs 8 User LEDs on-board Pin-compatible with FM-S651 series On-board, programmable clock generator with 4 output clocks, with available SSC

7 Research project overview 7 FX3 Firmware 18 February '13 USBpix Upgrade FX3 DVK Board USB 3.0 interface Firmware development FX3 device should be compatible with the software for the 8051 based USB 2.0 microcontroller FX3 device

8 Migrating from FX2 to FX3 8 Architectural Differences 18 February '13 USBpix Upgrade

9 Firmware development 9 18 February '13 USBpix Upgrade FX3 DVK Board Block Diagram

10 Firmware development February '13 USBpix Upgrade USB 3.0 Interface 4 endpoints for different transfer types were configured USB enumeration descriptors were configured DMA Manual channels were created between USB endpoints and CPU sockets FX3 is correctly recognized as SiUSB device on Windows 32 and 64-bit USB Device Manager interface

11 Firmware development February '13 USBpix Upgrade I 2 C EEPROM Configuration of the interface parameters (100 KHz bit rate, register transfer mode, no bus timeout, no DMA timeout) I2C transfer (preamble: the slave address, the direction of the transfer, the address inside the slave; wait for ACK) SPI SPI Flash Configuration of the interface parameters (8 MHz SPI clock, 8 bits word length, MSB first data shift mode, idles high clock polarity (CPOL = 1), clock phase (slave samples at active-idle edge (CPHA = 1)), active low polarity of SSN line, slave select using FW) SPI transfer (location: command, page address; set SSN line, erase sector, wait for status) Low performance peripherals (LPP)

12 Firmware development February '13 USBpix Upgrade FX3 – FPGA connectivity GPIF II (General Programmable Interface) Functions as master or slave Provides 256 firmware programmable states Supports 8 bit, 16 bit, and 32 bit parallel data bus Enables interface frequencies up to 100 MHz Supports 14 configurable control pins when 32 bit data bus is used. All control pins can be either input/output or bidirectional Supports 16 configurable control pins when 16 or 8 data bus is used. All control pins can be either input/output or bidirectional

13 Firmware development February '13 USBpix Upgrade GPIF II Designer Define the interface in the form of a state machine diagram The electrical interfacing details should be defined using the Interface definition tab before entering the state machine using the state machine canvas tab

14 Firmware development February '13 USBpix Upgrade GPIF II Designer

15 Firmware development February '13 USBpix Upgrade GPIF II Designer

16 Firmware development February '13 USBpix Upgrade IDLESOFWR_DATAEOFIDLE

17 Firmware development February '13 USBpix Upgrade GPIF II Designer GigaBee Header Baseboard with TE0600 module and cables to connect to FX3 FMU3-S6 series FPGA module

18 Firmware development 18 February '13 18 FMU3-S6 connected to the power supply, to the host through USB 3.0 interface and to the USB-JTAG Programming cable through the self-made connector. FX3 device: Can be programmed with software for the FX3 development kit (USB 3.0) FPGA: Can be programmed with JTAG interface (self-made connector + USB- JTAG Programming Cable) USBpix Upgrade

19 Firmware development 18 February '13 19 USBpix Upgrade Response from the FPGA (Timing)

20 Firmware development 18 February '13 20 GPIF II Designer (Timing simulation) USBpix Upgrade

21 Firmware development 18 February '13 21 Response from the FPGA to the reading access (FX3 delay) Response from the FPGA to the writing access (FX3 delay) USBpix Upgrade

22 Firmware development 18 February '13 22 Response from the FPGA to the reading access (FX3 + FPGA delay) Response from the FPGA to the writing access (FX3 + FPGA delay) USBpix Upgrade

23 Firmware development 18 February '13 23 ChipScope waveform (Writing to the FPGA) USBpix Upgrade

24 Conclusion February '13 USBpix Upgrade FX3 Firmware USB 3.0 GPIF II Writing to the FPGA Reading from the FPGA 4 endpoints for different transfer types were configured USB enumeration descriptors were configured DMA Manual channels were created between USB endpoints and CPU sockets Correctly recognized as SiUSB device on Windows 32 and 64-bit I 2 C EEPROM SPI SPI Flash

25 Conclusion February '13 USBpix Upgrade Next steps FPGA firmware (started) FX3 firmware (should be modified every time FPGA timing changes) PCB design of the new MultiIO Board

26 Contact Information February '13 USBpix Upgrade Viacheslav Filimonov

27 Backup February '13 USBpix Upgrade EZ USB FX3 System Diagram SPI Flash 4 Mbit EEPROM 64kB

28 Backup February '13 EZ USB FX3 System Diagram USBpix Upgrade

29 Backup February '13 USBpix Upgrade (Currently 8 MHz)

30 Backup February '13 USBpix Upgrade

31 Backup February '13 USBpix Upgrade Programming View of FX3

32 Backup February '13 USBpix Upgrade DMA Mechanism System Memory

33 Backup February '13 USBpix Upgrade DMA Components

34 Backup February '13 USBpix Upgrade USB Comparison

35 Backup 18 February '13 35 USBpix Upgrade Changes in USB 3.0 SuperSpeed — New higher signaling rate of 5Gbps (625MB/sec) Dual-bus architecture — Low-Speed, Full-Speed, and High-Speed bus plus SuperSpeed bus Asynchronous instead of polled traffic flow Dual-simplex simultaneous bi-directional data flow for SuperSpeed instead of half- duplex unidirectional data flow Support for streaming Fast Sync-N-Go technology Support for higher power Better power management

36 Backup 18 February '13 36 USBpix Upgrade USB 3.0 Pin Description Electrical Interface USB 3.0’s pinout is different from that of USB 2.0. Besides the VBUS, D-, D+, and GND pins required for 2.0, 3.0 has five additional pins – two differential pairs plus one ground (GND_DRAIN). The two differential pairs are for SuperSpeed data transfer, supporting dual simplex SuperSpeed signaling. The added GND_DRAIN pin is for drain wire termination, managing signal integrity, and EMI performance. For high throughput and biwire transfer, USB 3.0 defines nine pins to enhance this feature. These pins contain four pins for USB 2.0 and five additional pins for 3.0. Table 1 shows the description of these nine pins.


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