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JAZiO ™ Incorporated 1 JAZiO ™ Incorporated Digital Signal Switching Technology.

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Presentation on theme: "JAZiO ™ Incorporated 1 JAZiO ™ Incorporated Digital Signal Switching Technology."— Presentation transcript:

1 JAZiO ™ Incorporated 1 JAZiO ™ Incorporated Digital Signal Switching Technology

2 JAZiO ™ Incorporated 2 What is JAZiO Technology? A new method of interchip I/O switching –At high data rate with low latency –With low power –At low cost Effectiveness is due to using –Differential sensing with a single pin per bit –Built in timing –Look for change-of-data first –Transition detection

3 JAZiO ™ Incorporated 3 Traditional Signal Driving (Peak Detection) All information is transmitted during t RF (1/3 of bit time) The rest of the bit time is just wasted! One bit time Next bit time t RF t SU t HD Sharp Edges Cause: Ground Bounce! Cross Talk! Ringing! EMI! High Power!

4 JAZiO ™ Incorporated 4 Pseudo Differential Signal Sensing Sensing level about 1/3 of switching level The rest of the switching level is just wasted! Large switching levels cause: Ground Bounce! Cross Talk! Ringing! High Power! One bit time Next bit time Sensing Level V REF Switching Level  0.8V

5 JAZiO ™ Incorporated 5 JAZiO Solution JAZiO has invented a system which –Achieves very high performance –Has edges which can take the whole bit time –Detects data value as soon as transition occurs –Uses differential sensing with low signal levels –Yet has only 1 pin per data signal

6 JAZiO ™ Incorporated 6 What’s the Secret? A Re-think For each data signal, there is either a change or no-change from the previous bit time Traditional systems are good on no-change but bad on change JAZiO looks for change first and then adjusts if no-change occurs For JAZiO the decision binary is change or no-change rather than high or low voltage

7 JAZiO ™ Incorporated 7 JAZiO Solution Steering Logic Data Output VTR Data Input VTR B A Dual Comparators are used In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change Data is driven coincidentally with Voltage/Timing References Data Input VTR One Bit Time Provide alternating Voltage/Timing References switching at the data rate Next Bit Time 8 different combinations of VTR and Data Input 7 1 2 3 4 8 5 6

8 JAZiO ™ Incorporated 8 Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

9 JAZiO ™ Incorporated 9 Steering Logic Generate Steering Logic signals (SL and SL) Use them with Data Output from previous Bit Time to select between Comparators A and B Also use them for data latching SL Receiver Output XOR in out XOR in out Data Input VTR A B Latching System Latched Output

10 JAZiO ™ Incorporated 10 Data Output SL Initialization or Receiver Enable SL VTR Data Input Data Input XOR 55 Small Transistors Per Bit No PLL/DLL Required No die size penalty!!!

11 JAZiO ™ Incorporated 11 The receiver cell is: 22um x 55um (Including routing channels) The pad cell is: 70um x 80um

12 JAZiO ™ Incorporated 12 Time Domain Decision is made in the Time Domain rather voltage domain VTR Data Input First Look for change Determine no- change and switch to Comparator B  0.5V SL Data Output XOR in out XOR in out Data Input VTR A B

13 JAZiO ™ Incorporated 13 JAZiO ™ Receiver Operation A SL XOR-B Data Output in out Data Input VTR B XOR-A The No-change Cases Initialize 011001 Data Input Data Output VTR SL CompA CompB XOR-B XOR-A

14 JAZiO ™ Incorporated 14 Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). 3 Case 3: Comp A remains High past the point of change and the Data Output retains the previous data Case 1: Comp A amplifies the change and the data passes through the Steering Logic Change 1 The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output 1 THE GAP 1 THE GAP BECOMES INFINITE

15 JAZiO ™ Incorporated 15 The No-Change Case But! The handoff from Comparator A to B is smooth since both comparators and Data Output are all high After the handoff, Comparator B is ready to make the next differential comparison Since Comparator A is selected its high value causes Data Output to remain high Data Output XOR-B in out XOR-A SL Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high VTR Data Input VTR B A (High) Bit Time But eventually the SLs will switch causing the XORs to switch and Comparator B will be selected

16 JAZiO ™ Incorporated 16 vtr Data Input xnora Xnorb Data Output Time (nS) 456 0 1 1.8 Voltage (V) 4nH Package Break-Before-Make(Break-And-Remake)

17 JAZiO ™ Incorporated 17 Data Skew at Receiver Simulations show that width of Skew Band can be up to 40% of bit time VTR Data Input  500mV + 100mV - 150mV Recommended Skew band 1.25V/ns Bit time = 0.5ns

18 JAZiO ™ Incorporated 18 4 Bit JAZiO Receiver From Test Chip

19 JAZiO ™ Incorporated 19 16 JAZiO ™ Receivers From Test Chip

20 JAZiO ™ Incorporated 20 Transition Detection Higher frequency components, above the maximum operating frequency, can be filtered out at the receiver. Narrower voltage band for differential amplifier operation (  300mV). Self aligned data and VTRs shifts the steering logic time, latching window and change/no- change gap in real time relative to Vcc, temperature, manufacturing variations. Transition Detection Pseudo Differential Peak Detection Frequency components higher than the maximum frequency need to be present at the receiver (setup and hold time at VOH/VOL). Wider voltage band for differential amplifier operation is required (  600mV). Vref is a voltage average (Vcc, temperature and manufacturing, and noise). Clock is a time average based on PLL/DLL. Vref Band VH VL 600mV Diff Amp Band 300mV Diff Amp Band

21 JAZiO ™ Incorporated 21 2nH Package & ESD Model Low Pass Filter 0.6pf 1nH 0.24  Lead frame 0.6pf 1nH 0.2  Bond Wire 1pf N-Ch Clamp P-Ch Clamp 0.1pf Pad 0.1pf 200  C int To Receiver Input Protection Resistor

22 JAZiO ™ Incorporated 22 Simulation at 2Gb/s Middle of transmission line Package inductance 2nH Data Output VTR Data Input Time (nS) 56789 0 1 1.8 Voltage (V) Data Output VTR Data Input Time (nS) 56789 0 1 1.8 Voltage (V) At Pin At Receiver Input

23 JAZiO ™ Incorporated 23 Data Rate vs Slew Rate Comparison Slower edges Lower switching levels Reduced slew rate Slew Rate (V/nS) Data Rate per Pin (b/S) 10M 100M 1G 10G EDO-33 SDRAM-66 SDRAM-100 DDR RDRAM JAZiO™ Better Higher Performance at Lower Power with Higher Robustness

24 JAZiO ™ Incorporated 24 VTT Signal VTR VTT Signal VREF 1.VSSQ noise between signal and VREF 2.VTT noise and/or VTT mismatch on either end 3.VREF impedance to Signal impedance mismatch JAZiO Is Entirely Common-Mode JAZiO Pseudo Differential

25 JAZiO ™ Incorporated 25 Applying JAZiO Technology JAZiO is the physical I/O layer only –JAZiO provides no protocol –Works with any protocol –Like steel belted radial tires that work for Honda Civic, Ferrari Sports Car, or Ford Explorer Easy to use –No die size penalty –No PLL/DLL or special semiconductor technology –Low Power Can be used anywhere that fast switching or low power is useful

26 JAZiO ™ Incorporated 26 JAZiO for DRAM JAZiO Technology can be applied to scaled-up versions of existing protocols like DDR or RDRAM Or new protocols can be developed to match JAZiO’s low latency and high bandwidth to reduce pins and increase parallelism

27 JAZiO ™ Incorporated 27 16-Wide MP Server L3 BSB CONTROLLER FSB CPU 1GHz CPU I/O DRAM 2GHz Data Rate Quad Processor Module 2GHz Interprocessor Communication (Scalable to 4GHz) Quad Processor Module CPU L3 CPU L3 CPU L3 with 2GHz FSB & BSB All scalable to 2x frequencies

28 JAZiO ™ Incorporated 28 Notebook / Internet Appliance P avg = K  vVTTK  (Cf+1/R t ) Therefore Power Ratio = (0.5v1)/(0.8v1.8)   When compared to existing pseudo differential with VTT=1.8v, V LOW =1.0v, similar load capacitance, operating frequency and termination resistance Small swing and slower transition time reduces EMI allowing it to meet FCC limits for radiation SOCDRAM Power consumed in the memory interface is reduced due to low switching levels of V TT =1.0v and V LOW =0.5v JAZiO™

29 JAZiO ™ Incorporated 29 How Can JAZiO Be Used? JAZiO is “essentially” an Open Standard All technology is publicly visible w/o NDA Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes, etc Just don’t sell products without licensing it A JAZiO demonstration chip has been designed by Micro Magic, Inc – a JAZiO Design Services partner (

30 JAZiO ™ Incorporated 30 Conclusion JAZiO uses lower levels and slower edges Achieves high performance, low power, high robustness JAZiO technology is fundamentally different from traditional methods –Transition Detection rather than Peak Detection –Time domain rather than voltage domain –Look for change first –Change vs No-change rather than High or Low JAZiO is available to everyone at low cost and applies to any application

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