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* Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 1 * Pepe PICmicro  de 28.

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Presentation on theme: "* Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 1 * Pepe PICmicro  de 28."— Presentation transcript:

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2 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 1 * Pepe PICmicro  de 28

3 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 2 12-bit core 14-bit core 16-bit core 16-bit enh. core  33 instructions l Easy to learn l High compaction l Very powerful single-word instructions l All single- cycle except program branches l Upward compatibility of instructions  35 instructions  58 instructions  72+4 instructions R I S C

4 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 3 Byte-Oriented Operations Decrement f, skip if zero No Operation Move W to f Clear W Clear f Subtract W from f Decrement f Inclusive OR W and f AND W and f Exclusive OR W and f Add W and f Move f Complement f Increment f Rotate right f Rotate left f Swap halves f Increment f, skip if zero NOP- MOVWFf CLRW- CLRFf SUBWFf,d DECFf,d IORWFf,d ANDWFf,d XORWFf,d ADDWFf,d MOVFf,d COMFf,d INCFf,d DECFSZf,d RRFf,d RLFf,d SWAPFf,d INCFSZf,d Bit-Oriented Operations Bit clear f Bit set f Bit test f, skip if clear Bit test f, skip if set BCFf,b BSFf,b BTFSCf,b BTFSSf,b Literal and Control Operations Go into standby mode Clear Watchdog Timer Return, place Literal W Option Tris Port Call Subroutine Go to address Move Literal to W SLEEP CLRWDT RETLW OPTION TRISF CALL GOTO MOVLW - - k - f a a k AND Literal W Inclusive OR Literal W Exclusive OR Literal W ANDLW IORLW XORLW k k k f = file register address d = destination select a = program address b = bit k = literal Instrucciones PIC16C5X (33):

5 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 4 OP CODE Codificación instrucciones 12-bit Byte Oriented Operations OP CODE dfffff Bit Oriented Operations OP CODE bfffffbb k Literal Operations kkkkkkk OP CODE xaaa PC call and goto aaaaa

6 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 5 Indirect addr* TMR0 PCL STATUS FSR PORT A PORT B PORT C X X X X X Bank 0 Bank 1 Bank 2 Bank 3 * Not a physical register 00 0 F 10 1 F Mapa de Registros PIC16C5X

7 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 6 5-bit direct address from the instruction 2-bit from FSR register Effective 7-bit Register Address RA1RA0 OP CODE FSR Register 12-bit Instruction fffff RA1RA0fffff 5-bits From Instruction Word 2-bits From FSRRegister Direccionamiento Directo PIC16C5X

8 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 7 5-bit indirect address from the FSR (File Select Register). 2-bit from FSR register Effective 7-bit Register Address RA1RA0 FSR Register File Select Register fffff RA1RA0fffff 5-bits From FSR 2-bits From FSRRegister Direccionamiento Indirecto PIC16C5X

9 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 8 l Clear all RAM locations from 0x10 to 0x1F. l Indirect address is loaded into FSR. l Every time INDF is used as operand, register pointed to by FSR is actually used. l Clear all RAM locations from 0x10 to 0x1F. l Indirect address is loaded into FSR. l Every time INDF is used as operand, register pointed to by FSR is actually used. movlw0x10 movwfFSR LOOPclrfINDF incfFSR,F btfscFSR,4 gotoLOOP XXXX XXXX FSR = 10h INDF 00h 04h 10h 1Fh Data Memory Direccionamiento Indirecto PIC16C5X

10 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 9 GOTO: 9-bit destination address is loaded into PC. The upper 2-bit PC are loaded from STATUS allowing 4x512 (2K) addressing range. GOTO a a a a a a a a a PCL STATUS x p p x x x x x p p a a a a a a a a a GOTO: Salto Incondicional PIC16C5X

11 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 10 CALL: 8-bit destination address is loaded into PC. PC is forced to “0”. The upper 2-bit PC are loaded from STATUS allowing lower half of 4x512 (1K) addressing range. It means that all subrutine entry must be located in the lower half of any page. RETLW: PC is loaded from the top of the stack a a a a a a a a PCL STATUS x p p x x x x x p p 0 a a a a a a a a CALL CALL: Llamada a Rutina PIC16C5X

12 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 11 WRITE to PC: When the PC is the destination of any instruction, the computed 8-bit value will be loaded into PC. PC is forced to “0”. The upper 2-bit PC are loaded from STATUS allowing lower half of 4x512 (1K) addressing range. It means that any computed jump must be located in the lower half of any page. WRITE to PC d d d d d d d d PCL STATUS x p p x x x x x p p 0 a a a a a a a a Escritura en el PC: PIC16C5X

13 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 12 Byte-Oriented Operations Decrement f, skip if zero No Operation Move W to f Clear W Clear f Subtract W from f Decrement f Inclusive OR W and f AND W and f Exclusive OR W and f Add W and f Move f Complement f Increment f Rotate right f Rotate left f Swap halves f Increment f, skip if zero NOP MOVWF CLRW CLRF SUBWF DECF IORWF ANDWF XORWF ADDWF MOVF COMF INCF DECFSZ RRF RLF SWAPF INCFSZ - f - f f,d Bit-Oriented Operations Bit clear f Bit set f Bit test f, skip if clear Bit test f, skip if set BCFf,b BSFf,b BTFSCf,b BTFSSf,b Literal and Control Operations Go into standby mode Clear Watchdog Timer Return, place Literal W Return from interrupt Return Call Subroutine Go to address Move Literal to W Add Literal to W Subtract Literal from W AND Literal W Inclusive OR Literal W Exclusive OR Literal W SLEEP CLRWDT RETLW RETFIE RETURN CALL GOTO MOVLW ADDLW SUBLW ANDLW IORLW XORLW - - k - - a a k k k k k k f = file register address d = destination select a = program address b = bit k = literal Instrucciones PIC16FXXX (35):

14 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 13 Codificación instrucciones 14-bit Byte Oriented Operations OP CODE dfffffff Bit Oriented Operations OP CODE bfffffffbb k Literal Operations OP CODE kkkkkkk aaaa PC call and goto aaaaaaa

15 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 14 * Not a physical register Bank 2 Bank 3 FF 7F Indirect addr* OPTION PCL STATUS FSR TRIS A TRIS B X PCLATH INTCON X Bank 1 Indirect addr* TMR0 PCL STATUS FSR PORT A PORT B X PCLATH INTCON X Bank 0 Mapa de Registros PIC16FXXX

16 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 15 7-bit direct address from the instruction 2-bit from STATUS register Effective 9-bit Register Address IRPRP1RP0 OP CODE TOPDZDCC STATUS Register 14-bit Instruction fffffff RP1RP0fffffff 7-bits From Instruction Word 2-bits From STATUSRegister Direccionamiento Directo PIC16FXXX

17 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 16 IRPffffffff f 8-bit indirect address from the FSR (File Select Register). 1-bit from STATUS register. 8-bit indirect address from the FSR (File Select Register). 1-bit from STATUS register. IRPRP1RP0TOPDZDCCfffffff STATUS Register 8-bit FSR Register Effective 9-bit Register Address 8-bits From FSR 1-bit From STATUSRegister Direccionamiento Indirecto PIC16FXXX

18 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 17 l Clear all RAM locations from 0x20 to 0x7F. l Indirect address is loaded into FSR. l Every time INDF is used as operand, register pointed to by FSR is actually used. l Clear all RAM locations from 0x20 to 0x7F. l Indirect address is loaded into FSR. l Every time INDF is used as operand, register pointed to by FSR is actually used. movlw0x20 movwfFSR LOOPclrfINDF incfFSR,F btfssFSR,7 gotoLOOP FSR = 20h INDF 00h 04h 20h 7Fh Data Memory Direccionamiento Indirecto PIC16FXXX

19 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 18 l 8-bit constant (literal) value included in instruction word. l Used by literal instructions such as movlw, addlw, retlw, etc. l 8-bit constant (literal) value included in instruction word. l Used by literal instructions such as movlw, addlw, retlw, etc. OP CODE k 14-bit Instruction for Literal Instructions kkkkkkk Direccionamiento Inmediato PIC16FXXX

20 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 19 xxxppxxx ppaaaaaaaaaaa GOTO: 11-bit destination address is loaded into PC. The upper 2-bit PC are loaded from PCLATH allowing 4x2K (8K) addressing range. PCLATH GOTO: Salto Incondicional PIC16FXXX OP CODE aaaaaaaaaaa Program Counter

21 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 20 xxxppxxx ppaaaaaaaaaaa CALL: 11-bit destination address is loaded into PC. The upper 2-bit PC are loaded from PCLATH allowing 4x2K (8K) addressing range. PCLATH CALL: Llamada a Rutina PIC16FXXX OP CODE aaaaaaaaaaa Program Counter RETLW, RETURN and RETFIE: PC is loaded from the top of the stack. PCLATH is unchanged.

22 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 21 PCH PCH PCL PCL 13-Bit Program Counter PCLATH PCLATH Internal Data Bus Internal Data Bus l First write high byte to PCLATH. l Next write low byte to PCL, this loads the entire 13-bit value to PC. l Reading the PC l Read low byte from PCL from PCL l PCLATH is NOT loaded with loaded with value from PCH value from PCH Direccionamiento Relativo PC PIC16FXXX l Used to perform a computed goto by adding an offset directly to the 13-bit Program Counter (8K addressing).

23 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 22 Do NOT use OPTION AND TRIS instructions Do NOT use OPTION AND TRIS instructions on 14 bit core devices. on 14 bit core devices. These Instructions are not in the 12 bit core: These Instructions are not in the 12 bit core: ADDLW - Add literal k to contents of W register SUBLW - Subtract W from Literal RETURN - Return from subroutine RETFIE - Return from interrupt subroutine Instrucciones 12-bit 14-bit

24 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 23 Byte-Oriented Operations No Operation NOP - Clear f CLRF f,s Set f SETF f,s Move W to f MOVWF f Move f to p MOVFP f,p Move p to f MOVPF p,f Negate W NEGW f,s Complement f COMF f,d AND W with f ANDWF f,d Incl OR W with f IORWF f,d Excl OR W with f XORWF f,d Add W with f ADDWF f,d Add W with f + CY ADDWFC f,d Sub W with f SUBWF f,d Sub W with f + BW SUBWFB f,d Decimal Adjust W DAW f,s Swap f SWAPF f,d Multiply W with f MULWF f Byte-Oriented Operations f / p = file / peripheral register address t = Table latch high or low tranfer d / s = destination select i = Autoincrement pointer a = program address b = bit k = literal Decrement f DECF f,d Decr f skip if ZR DECFSZ f,d Decr f skip if NZR DCFSNZ f,d Increment f INCF f,d Incr f skip if ZR INCFSZ f,d Incr f skip if NZR INFSNZ f,d Comp f-W skip if = CPFSEQ f Comp f-W skip if > CPFSGT f Comp f-W skip if < CPFSLT f Test f skip if ZR TSTFSZ f Rotate left f with CY RLCF f,d Rotate left f without CY RLNCF f,d Rotate right f with CY RRCF f,d Rotate right f without CY RRNCF f,d Table read TABLRD t,i,f Table write TABLWT t,i,f Table latch read TLRD t,f Table latch write TLWT t,f Instrucciones PIC17CXXX (58):...

25 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 24 Bit-Oriented Operations Bit clear f BCF f,b Bit set f BSF f,b Bit toggle f BTG f,b Bit test skip 0 BTFSC f,b Bit test skip 1 BTFSS f,b Literal and Control Operations f / p = file / peripheral register address t = Table latch high or low tranfer d / s = destination select i = Autoincrement pointer a = program address b = bit k = literal Move literal to W MOVLW k Move literal low BSR MOVLB k Move literal high BSR MOVLR k AND literal with W ANDLW k Incl OR literal with W IORLW k Excl OR literal with W XORLW k Add literal with W ADDLW k Sub literal with W SUBLW k Multiply Lit with W MULLW k Go to address GOTO a Subrutine call CALL a Subrutine Long call LCALL a Return literal to W RETLW k Return subrutine RETURN - Return from int. RETFIE - Clear Watchdog CLRWDT - Go to standby mode SLEEP -... Instrucciones PIC17CXXX (58):

26 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 25 Byte-Oriented & Literal Add literal with WregADDLWk Add Wreg with fADDWFf,d,a Add Wreg with f + carryADDWFCf,d,a And literal with WregANDLWk And Wreg with fANDWFf,d,a Clear fCLRFf,a Complement fCOMFf,d,a Compare f with Wreg, skip if =CPFSEQf,a Compare f with Wreg, skip if >CPFSGTf,a Compare f with Wreg, skip if

27 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 26 Control operations Branch if carryBCn Branch if no carryBNCn Branch if negativeBNn Branch if no negative BNNn Branch if overflowBOVn Branch if no overflow BNOVn Branch if zeroBZn Branch if no zeroBNZn Branch unconditionallyBRAn Go to addressGOTOp Relative callRCALLn Call subroutineCALLp,s Return from subroutineRETURNs Return with literal in WregRETLWk Return from interrupt enableRETFIEs Pop top of return stackPOP Push top of return stackPUSH No operationNOP No operation 2nd word Clear watchdog timerCLRWDT Change into standby modeSLEEP Software device resetRESET... Instrucciones PIC18FXXXX (76): Bit clear into fBCFf,b,a Bit set into fBSFf,b,a Bit toggle into fBTFf,b,a Bit test f, skip if clearBTFSCf,b,a Bit test f, skip if setBTFSSf,b,a Table read TBLRD* Table read with pre-increment TBLRD+* Table read with post-increment TBLRD*+ Table read with post-decrement TBLRD*- Table write TBLWT* Table write with pre-increment TBLWT+* Table write with post-increment TBLWT*+ Table write with post-decrement TBLWT*- Bit-Oriented Data Program Memory f = file register addressd = destination selecta = banck select n&p = program addressb = bit k = literal s = shadow reg.

28 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 27 CLRWDT: Watchdog timer and its postscaler are cleared. /TO = 1 and /PD = 1 If WDT overflow resets the chip Instrucciones Especiales de los PICs CLRWDT Overflow Resets Chip 8-bit Ripple CounterPostscaler CLRWDT Internal free-running RC Oscillator ‘0’

29 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 2-INSTR / 28 Instrucciones Especiales de los PICs SLEEP The processor can be put into a power-down mode by executing the SLEEP instruction. –System oscillator is stopped. –Processor status is maintained (static design). –I/O pins configured as output will continue to drive –Wake-up (WDT) and its postscaler are cleared. –/TO = 1 and /PD = 0. –Wake-up (WDT) timer continues to run, if enabled. –Minimal supply current is drawn - mostly due to leakage. –Power-Down Current:  A typical. –Device remain in power down until any wake-up. OSC1 OSC2 SLEEP Osc. Disable


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