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Slide title minimum 48 pt Slide subtitle minimum 30 pt Three Verification Challenges Hans Lundén Digital ASIC Manager Functional Verification.

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Presentation on theme: "Slide title minimum 48 pt Slide subtitle minimum 30 pt Three Verification Challenges Hans Lundén Digital ASIC Manager Functional Verification."— Presentation transcript:

1 Slide title minimum 48 pt Slide subtitle minimum 30 pt Three Verification Challenges Hans Lundén Digital ASIC Manager Functional Verification

2 Slide title minimum 32 pt (32 pt makes 2 rows Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt !"#$%&'()*+,-./ :; UVWXYZ[\]^_`abcdefghijklmnopqrstuvwxy z{|}~¡¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍ ÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñ òóôõö÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚ ěĞğĠġĢģĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗ ŘřŚśŞşŠšŢţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘ ˙˚˛˜˝ẀẁẃẄẅỲỳ–—‘’‚“”„†‡…‰‹›⁄€™−≤≥fifl ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞĠĠĢĢĪĪĮĮİĶĶĹ ĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤŤŪŪŮŮŰŰ ŲŲŴŴŶŶŹŹŻŻȘș ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊ ΰαβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐ Ґә ǽ ẀẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Three Challenges | Public | © Ericsson AB 2011 | | Page 2 CHallenges? ›Verification challenge areas –Quantity of verification work (Integration, complexity) –Difficulty of verification work (Complexity) –Efficiency (Quality vs TTM and cost) –VIP –Power management –Exit criteria (Efficiency) –Languages/Methodologies/Tools –Design/Systemization for Verification –TLM in Verification –….

3 Slide title minimum 32 pt (32 pt makes 2 rows Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt !"#$%&'()*+,-./ :; UVWXYZ[\]^_`abcdefghijklmnopqrstuvwxy z{|}~¡¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍ ÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñ òóôõö÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚ ěĞğĠġĢģĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗ ŘřŚśŞşŠšŢţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘ ˙˚˛˜˝ẀẁẃẄẅỲỳ–—‘’‚“”„†‡…‰‹›⁄€™−≤≥fifl ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞĠĠĢĢĪĪĮĮİĶĶĹ ĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤŤŪŪŮŮŰŰ ŲŲŴŴŶŶŹŹŻŻȘș ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊ ΰαβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐ Ґә ǽ ẀẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Three Challenges | Public | © Ericsson AB 2011 | | Page 3 TLM in verification ›Started to use TLM to model ASIC functionality and its environment. –Both LT and AT models are used for several purposes. ›System development. ›Early SW development. ›Early system performance investigations ›Planned to be introduced also in verification. –Early verification test bench and test case development. ›Why? –TTM (Time To Market)

4 Slide title minimum 32 pt (32 pt makes 2 rows Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt !"#$%&'()*+,-./ :; UVWXYZ[\]^_`abcdefghijklmnopqrstuvwxy z{|}~¡¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍ ÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñ òóôõö÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚ ěĞğĠġĢģĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗ ŘřŚśŞşŠšŢţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘ ˙˚˛˜˝ẀẁẃẄẅỲỳ–—‘’‚“”„†‡…‰‹›⁄€™−≤≥fifl ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞĠĠĢĢĪĪĮĮİĶĶĹ ĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤŤŪŪŮŮŰŰ ŲŲŴŴŶŶŹŹŻŻȘș ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊ ΰαβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐ Ґә ǽ ẀẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Three Challenges | Public | © Ericsson AB 2011 | | Page 4 Verification IP ›Internal VIPs –Develop in house or outsource? –Takes time. New VIPs is always a risk. ›Standard VIP –Purchase or develop? ›Decision from case to case. ›VIP business not as mature as Design IP business. ›Quality problems in VIPs often revealed very late in projects. ›Why? –Quality.

5 Slide title minimum 32 pt (32 pt makes 2 rows Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt !"#$%&'()*+,-./ :; UVWXYZ[\]^_`abcdefghijklmnopqrstuvwxy z{|}~¡¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍ ÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñ òóôõö÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚ ěĞğĠġĢģĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗ ŘřŚśŞşŠšŢţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘ ˙˚˛˜˝ẀẁẃẄẅỲỳ–—‘’‚“”„†‡…‰‹›⁄€™−≤≥fifl ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞĠĠĢĢĪĪĮĮİĶĶĹ ĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤŤŪŪŮŮŰŰ ŲŲŴŴŶŶŹŹŻŻȘș ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊ ΰαβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУ ФХЦЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐ Ґә ǽ ẀẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Three Challenges | Public | © Ericsson AB 2011 | | Page 5 Design for Verification ›“Design” is here including System down to RTL: –RTL level ›Code to support verification. –Block architecture ›Partitioning of functions and choice of interfaces between sub blocks that simplifies verification –ASIC level ›Re-use ›Minimize number of unique interfaces ›Minimize number updated blocks –System and product mgmt level ›Minimize number of unique interfaces ›Minimize number of updated functions ›Why? –Quality and TTM

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