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Speaker: Bob Tsai Advisor: Jie-Hong Roland Jiang.

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Presentation on theme: "Speaker: Bob Tsai Advisor: Jie-Hong Roland Jiang."— Presentation transcript:

1 Speaker: Bob Tsai Advisor: Jie-Hong Roland Jiang

2  Introduction  Flow  On Chip Variation (OCV)  Manual/automated netlist editing  Signal integrity and crosstalk

3  PrimeTime VX, PrimeTime SI  Sign-off ◦ A collective name to a series of verification steps  Standard Parasitic Exchange Format ◦ Represent parasitic data of wires in a chip in ASCII format ◦ Used for delay calculation and ensuring the signal integrity

4 Setup Design Create CHIP constraints CHIP level STA P&R Tape-out Timing error? Update SDC Update RTL pass fail Check setup Validate Prelayout Constraints Validate Constraints Hand-off Validate Postlayout Constraints Update SDC fail pass

5  Models the small difference in operating parameters across the chip  Setup check: max delay for data path and min delay for clock path  Hold check: min delay for data path and max delay for clock path

6 D Q logic CT3 CT2 CT1 CLK 0.48/ / /0.65 max = 3.04/3.8 min = 1.6/2.0 Clock path 1 = =1.4 Data path max = 3.8 Clock path 2 = =1.16 Setup = 0.2 => The clock period must be at least =4.24 setup = 0.2

7 D Q logic CT3 CT2 CT1 CLK 0.48/ / /0.65 max = 3.04/3.8 min = 1.6/2.0 hold = 0.1

8 CommandsMain functions set_wire_load_model(before P&R) read_sdf(after P&R) read_parasitics(after P&R) check_timingChecks for constraint problem such as undefined clocking, input data arrival times, and output data required times. (must-do) report_designLists the attributes of the design, including the chosen operating conditions, wire load information, and design rules. report_clockGenerates a report on the clocks defined for the design, showing for each clock the name, period, rise and fall times, and timing characteristics such as latency and uncertainty.

9  size_cell  insert_buffer | remove_buffer  swap_cell  Use write_change to output the changes

10  The design should be fully placed and routed, including clock trees, but without corefiller  fix_eco_timing –type {setup | hold}  fix_drc_timing –type {max_transition | max_capacitance | max_fanout} –method {size_cell | insert_buffer} pt_shell> fix_drc_timing –type max_transition –method {size_cell} -verbose pt_shell> fix_drc_timing –type max_transition –method {insert_buffer} -buffer_list {BUFX1 BUFX2 BUFX3} -verbose

11  Signal integrity ◦ The ability of an electrical signal to carry information reliably and resist the effects of high- frequency electromagnetic interference from nearby signals  Crosstalk ◦ The undesirable electrical interaction between two or more physically adjacent net due to capacitive cross-coupling



14 set_false_path set_false_path –from CLK1 –to CLK2 set_false_path –from CLK2 –to CLK1 set_false_path –from CLK3 –to CLK4 set_false_path –from CLK4 –to CLK3 set_false_path –from CLK1 –to CLK4 set_false_path –from CLK4 –to CLK1 set_false_path –from CLK2 –to CLK3 set_false_path –from CLK3 –to CLK2 set_clock_group set_clock_groups \ -logically_exclusive –name E1 \ -group {CLK1 CLK3} -group {CLK2 CLK4} set_active_clock [all_clocks] D Q CLK1 CLK2 SEL 0 1 CLK3 CLK4 0 1 D Q logic

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