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XILINX CONFIDENTIAL. Design AXI Master Page 1. XILINX CONFIDENTIAL. Understanding Zynq AXI Master IP axi_user_npi Page 2 Agenda © Copyright 2012 Xilinx.

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Presentation on theme: "XILINX CONFIDENTIAL. Design AXI Master Page 1. XILINX CONFIDENTIAL. Understanding Zynq AXI Master IP axi_user_npi Page 2 Agenda © Copyright 2012 Xilinx."— Presentation transcript:

1 XILINX CONFIDENTIAL. Design AXI Master Page 1

2 XILINX CONFIDENTIAL. Understanding Zynq AXI Master IP axi_user_npi Page 2 Agenda © Copyright 2012 Xilinx

3 XILINX CONFIDENTIAL. AXI is Part of AMBA: Advanced Microcontroller Page 3 What is AXI? © Copyright 2012 Xilinx Variations of AXI

4 XILINX CONFIDENTIAL. AXI4 –Memory mapped Page 4 Variations of AXI © Copyright 2012 Xilinx AXI4-Lite: –Register mapped AXI4-Stream: –Streaming

5 XILINX CONFIDENTIAL. Page 5 Why Xilinx Choose AXI? © Copyright 2012 Xilinx Page 5 External Memory External Memory Timer SRAM UART GPIO Microblaze BRAM LMB MPMC PLBv46 Video TEMAC Custom IP VFBC Local Link NPI PLB to IPIF Bridge PLB to IPIF Bridge Custom IP IPIF Xilinx Cache Link Hardware Accelerator Hardware Accelerator FSL

6 XILINX CONFIDENTIAL. Page 6 Why Xilinx Choose AXI? © Copyright 2012 Xilinx Page 6 External Memory External Memory Timer SRAM UART GPIO Microblaze BRAM LMB MPMC AXI Video TEMAC Custom IP AXI AXI to IPIF Bridge AXI to IPIF Bridge Custom IP IPIF AXI Hardware Accelerator Hardware Accelerator AXI

7 XILINX CONFIDENTIAL. Channel –Read address –Write address –Read data –Write data –Write response Page 7 AXI Protocol, Channel © Copyright 2012 Xilinx

8 XILINX CONFIDENTIAL. Page 8 AXI Protocol, AXI4 © Copyright 2012 Xilinx Single address multiple data –Burst up to 256 data beats Data width parameterizable –32, 64, 128, 256 AXI4 READ AXI4 Write

9 XILINX CONFIDENTIAL. Page 9 AXI Protocol, AXI4_LITE © Copyright 2012 Xilinx Single address Single data –No Burst Data width –32 AXI4-Lite Read AXI4-Lite Write

10 XILINX CONFIDENTIAL. Page 10 AXI Protocol, AXI4_STREAM © Copyright 2012 Xilinx No address channel Not read and write, always just master to slave Unlimited burst length

11 XILINX CONFIDENTIAL. Page 11 ZYNQ © Copyright 2012 Xilinx High Performance Port General Performance Port AXI Master AXI Slave

12 XILINX CONFIDENTIAL. Page 12 How to Design AXI Master © Copyright 2012 Xilinx CIP Select AXI type Select Master

13 XILINX CONFIDENTIAL. Page 13 How to Design AXI Master, example MPD –Default parameter PAO –Order for synthesis TEST_IP.VHD –Top level USER_LOGIC.VHD –User logic

14 XILINX CONFIDENTIAL. Page 14 How to Design AXI Master User_logic.vhd –Control Burst Transaction

15 XILINX CONFIDENTIAL. Page 15 Why Design AXI Master To access DDRx Memory Why don’t you use BRAM? Because BRAM is EASY But BRAM is TOO SMALL DDRx is LARGE But DDRx is not EASY DDRx max 1GB Zynq Bram 220KB ~ 2180KB

16 XILINX CONFIDENTIAL. Page 16 FIFO Instead of IPIC © Copyright 2012 Xilinx Remove Complexity

17 XILINX CONFIDENTIAL. Page 17 Master IP with FIFO, axi_user_npi © Copyright 2012 Xilinx IP catalog Bus Port

18 XILINX CONFIDENTIAL. Page 18 Master IP with FIFO, axi_user_npi © Copyright 2012 Xilinx User logic interface –Simple –It is FIFO component system is port (... wr_fifo_wr_en : in std_logic; wr_fifo_clk : in std_logic; npi_wr_ready : out std_logic; rd_fifo_rd_en : in std_logic; npi_rd_ready : out std_logic; wr_fifo_data : in std_logic_vector(31 downto 0); rd_fifo_clk : in std_logic; rd_fifo_full : out std_logic; rd_fifo_data : out std_logic_vector(31 downto 0); rd_fifo_empty : out std_logic; wr_fifo_full : out std_logic; wr_fifo_empty : out std_logic ); end component;

19 XILINX CONFIDENTIAL. Page 19 Master IP with FIFO, axi_user_npi © Copyright 2012 Xilinx How to Run? –Device Driver Read –Start add –Read Burst Cnt –Repeat Cnt Write –Start add –Read Burst Cnt –Repeat Cnt void npi_stop() { } void npi_start() { } void axi_npi_rd(int reg, int src, int cnt_burst, int cnt_repeat) { } void axi_npi_wr(int reg, int src, int cnt_burst, int cnt_repeat) { } void axi_npi_reset0() { } int npi_status(int reg) { }

20 XILINX CONFIDENTIAL. Page 20 Simulation Result © Copyright 2012 Xilinx Burst Write Burst Read

21 XILINX CONFIDENTIAL. Page 21 Q&A © Copyright 2012 Xilinx


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