Presentation on theme: "ECE Fault Testable Design Dr. Janusz Starzyk"— Presentation transcript:
1 ECE 617 - Fault Testable Design Dr. Janusz Starzyk School of EECSOhio UniversityAthens, OH, 45701Partially based on Prof. Vishwani D. Agrawal lecture VLSI Testingand book by S. Mourad, Y. Zorian, "Principles of Testing Electronic Systems”
6 Outline 0.18u VLSI silicon neurons Reliability and testing Reliability and testingDesign ProcessVerification & testingFaults and their detectionFault coverageTypes of testsTest applicationsDesign for TestTest economics
7 Reliability and Testing Reliability of electronics systems is no longer limited to military, aerospace or bankingUsed by almost everyone in the workplaceApplied to smaller and smaller devicesHave continually new failure modesReliability depending on being error freeFailures in both software and hardwareHere we concentrate on hardware
8 Test ObjectiveThe goal over time is to reduce the cost of manufacturing the product by reducing the per-part recurring costs:- reduction of silicon cost by increasing volume and yield, and by die size reduction (process shrinks or more efficient layout)- reduction of packaging cost by increasing volume, shifting to lower cost packages if possible (e.g., from ceramic to plastic), or reduction in package pin count
9 Test Objective - reduction in cost of test by: - reducing the vector data size- reducing the tester sequencing complexity- reducing the cost of the tester- reducing test time- simplifying the test program
11 Verification and Testing Testing a circuit prior to fabrication is known as design verificationVerification is certainly done at various stages of the design processMost viable design verification is through simulationTesting is identifying that the fabricated circuit is free from errorsNeed to specify what errors testing is looking for
18 Faults and their Detection Physical failures are manifested as electrical failures and are interpreted as faults on the logic levelSeveral physical defects may be mapped into few fault typesThe main fault type is Stuck-at FaultA fault is detected by a test patternTest pattern is an input combination that confirms the presence of the fault
19 Possible DefectsTwo technologies, two physical defects map into the same stuck-at zero faultNotation used - A SA0, or A/0
20 Detecting Stuck-at Faults BZFill in the blanks infaulty response A/0 and A/1InputsFFFaulty ResponseABResponseA/0B/0Z/0A/1B/1Z/100101101111
26 Types of TestsThe exhaustive test used to detect the faults on a 2-input AND gate is not practical for circuits with 20 or more primary inputsPseudo-exhaustive: exhaustive for components in the circuitssegmentation or partitioningA random test is also viable to detect faults, but pseudo-exhaustive tests are more realistic for Stuck-at FaultsDeterministic or fault oriented tests
27 Functional Testing Exhaustive & pseudo-exhaustive testing : Partial dependence circuits:a circuit in which primary outputs (PO)depend on all the primary inputs (PI)- each output tested using 2ni inputs(ni < n shows inputs affecting PO)
28 Functional Testing Exhaustive & pseudo-exhaustive testing Example : for each gate
29 Functional TestingExhaustive & pseudo-exhaustive testing Partitioning technique :the circuit is partitioned into segments such that each segment has small number of inputseach segment is tested exhaustivelyusually inputs & output of each segment are not PIs or POs so we need to control segment inputs using PIs and observe its outputs using PO - this lead to sensitizing partitioning
30 Functional TestingExample : Consider the following circuit :
31 Functional Testing Example: the following shows 8 input vectors to test exhaustively h.
32 Functional Testing Example: Add vectors 5 - 8 to test exhaustively g and to test exhaustively y
33 Functional Testing Example: Add missing combinations to vectors 4 and 9 to test exhaustively x
34 Types of Testing Verification testing, characterization testing Verifies correctness of design and correctness of test procedureMay require correction of either or bothManufacturing testingFactory testing of all manufactured chips for parametric and logic faults, and analog specificationsBurn-in or stress testingAcceptance testing (incoming inspection)User (customer) tests purchased parts to ensure quality
35 Verification Test Very expensive May comprise: Applied to selected partsUsed prior to production or manufacturing testMay comprise:Scanning Electron Microscope testsBright-Lite detection of defectsElectron beam testingArtificial intelligence (expert system) methodsRepeated functional tests
36 Manufacturing TestDetermines whether manufactured chip meets specificationMust cover high % of modeled faultsMust minimize test time (to control cost)No fault diagnosisTest at rated speed or at maximumspeed guaranteed by supplier
38 Burn-in or Stress Test Process: Catches infant mortality cases Subject chips to high temperature and over-voltage supply, while running production testsCatches infant mortality casesThese are damaged or weak (low reliability) chips that will fail in the first few days of operationBurn-in causes bad devicesto fail before they areshipped to customers
39 Manufacturing Test Scenarios Wafer sort or probe testDone before wafer is scribed and cut into chipsTest devices are checked with specific patterns to measure:Gate thresholdPolysilicon field thresholdPoly sheet resistance, etc.Packaged device tests
40 Types of TestsParametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheapFunctional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive
41 Functional TestATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing testAutomatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)
42 Levels of testing Levels Cost – Rule of 10 Chip Board System Boards put togetherSystem-on-Chip (SoC)System in fieldCost – Rule of 10It costs 10 times more to test a device as we move to higher levels in the product manufacturing processMixed Signal VLSI CircuitBe sure everyone has a conduct sheet.Re GROUND RULES:1. In terms of allowed collaboration vs. individual work, ask if you are not sure.2. Deactivate all cell phones or pagers during class unless you are on-call during your job.3. No tape-recording permitted. Take notes.
43 Levels of testingOther ways to define levels – these are important to develop correct “fault models” and “simulation models”TransistorGateRTLFunctionalBehavioralArchitectureFocus: Chip level testing– gate level designBe sure everyone has a conduct sheet.Re GROUND RULES:1. In terms of allowed collaboration vs. individual work, ask if you are not sure.2. Deactivate all cell phones or pagers during class unless you are on-call during your job.3. No tape-recording permitted. Take notes.
44 Typical Test Program Probe test (wafer sort) Contact electrical test Catches gross defectsContact electrical testFunctional & layout-related testDC parametric testAC parametric testUnacceptable voltage/current/delay at pinUnacceptable device operation limits
47 Propagation Delay Tests Apply standard output pin load (RC or RL)Apply input pulse with specific rise/fallMeasure propagation delay from input to outputDelay between 5 ns and 40 ns (ok)Delay outside range (fails)
48 On Line Testing Embedded checkers – error detection Periodic diagnostic programsWatchdog checkers
50 Test Specifications & Plan Functional CharacteristicsType of Device Under Test (DUT)Physical Constraints – package, pin numbers, etc.Environmental Characteristics – power supply, temperature, humidity, etc.Reliability – acceptance quality level (defects/million), failure rate, etc.Test plan generated from specificationsType of test equipment to useTypes of testsFault coverage requirement
51 Test Data Analysis Uses of ATE test data: Reject bad DUTsFabrication process informationDesign weakness informationDevices that did not fail are good only if tests covered 100% of faultsFailure mode analysis (FMA):Diagnose reasons for device failure, and find design and process weaknessesImprove logic and layout design rules
52 Cost of TestingTesters cost over$VLSI Test System TS600
53 Cost of Testing Design for testability (DFT) Chip area overhead and yield reductionPerformance overheadSoftware processes of testTest generation and fault simulationTest programming and debuggingManufacturing testAutomatic test equipment (ATE) capital costTest center operational cost
54 Cost of Manufacturing Testing Example test cost:GHz, analog instruments,1024 digital pins: ATE purchase price= $4.272MRunning cost (five-year linear depreciation)= Depreciation + Maintenance + Operation= $0.854M + $0.085M + $0.5M= $1.439M/yearTest cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= 4.5 cents/second
68 Multi-site TestingOne ATE tests several (usually identical) devices at the same timeBoth probe and package testDUT interface board has > 1 socketsUsually tests 2 or 4 DUTS at a timeUsually test 32 or 64 memory chips at a timeLimits: # instruments available in ATE, type of handling equipment available for package
69 Example VLSI Test Systems Advantest T3347BLow-cost Parallel Testing ofFour High-end MCU andTesting of Large ASIC40 MHZ testing speed.Accommodates up to 512 I/O pins.Simultaneous testing of up to fourdevices per station.
72 T6682 ATE Specifications Uses 0.35 mm VLSI chips in implementation 1024 pin channelsSpeed: 250, 500, or 1000 MHzTiming accuracy: +/- 200 psDrive voltage: -2.5 to 6 VClock/strobe accuracy: +/- 870 psClock settling resolution: psPattern multiplexing: write 2 patterns in one ATE cyclePin multiplexing: use 2 pins to control 1 DUT pin
73 T6682 Pattern Generation Sequential pattern generator (SQPG): stores 16 M vectors of patterns to apply to DUT,vector width determined by # DUT pinsAlgorithmic pattern generator (ALPG):32 independent address bits,36 data bitsScan pattern generator (SCPG)supports JTAG boundary scan,greatly reduces test vector memory for full-scan testing
74 T6682 Test Data Analysis Uses of ATE test data: Reject bad DUTSFabrication process informationDesign weakness informationDevices that did not fail are good only if tests covered 100% of faultsFailure mode analysis (FMA)Diagnoses reasons for device failureFinds design and process weaknessesAllows improvement of logic & layout design rules
75 T6682 Probe CardProbe card – custom printed circuit board (PCB) on which DUT is mounted in socketmay contain custom measurement hardwareProbe needlescome down and scratch the pads to stimulate/read pinsMembrane probe – for unpackaged waferscontacts printed on flexible membrane, pulled down onto wafer with compressed air
77 Specifications Intended for SOC test Modular enVision Operating System digital, analog, and memory testsupports scan-based testModularcan be upgraded with additional instrumentsenVision Operating Systemmaximum 64 M vectors memory storage1 or 2 test heads per tester, maximum of 1024 digital pins, 1 GHz maximum test rateAnalog instruments:DSP-based synthesizers, digitizers, time measurement, power test, radio frequency source and measurement capability (up to 4.3 GHz)
78 ADVANTEST Model T2000 ATE Scalable Architecture Microsoft Windows 2000 C++(Microsoft Visual Studio Professional)OTPL(Open Architecture Test System Programming Language)Re-configurable Program Structure for test data and algorithmT2000 System Software EmulatorWave Tool (Logic Analyzer, Oscilloscope).
79 ADVANTEST T6577 Tests SoC/Mixed-Signal Devices Supports for a maximum of 1024 logic and/or I/O channels.Performs parallel test of up to 32 devicesSupports baseband, DVD read channel, and jitter testAt-speed test of high-speed memory interfacesTest rates of up to 667 Mbpsmaximum of eight channels
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