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Triana Single Design Review

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Presentation on theme: "Triana Single Design Review"— Presentation transcript:

1 Triana Single Design Review
TRIANA COMPUTATION HUB Quang Nguyen/Code 561 NASA/Goddard Space Flight Center Triana SDR June 7 - 9, 1999 Computation Hub

2 Computation Hub Changes from SMEX-LITE design
Make design modification on the CIS to meet Triana requirements: Add variable Transponder Mod Index selections based on previous SMEX design Change downlink data rates from four rates (4, 2, .5 and .25 Mbps) to the wide range of programmable rates (from 4 Mbps to 300 bps) Add the Reed-Solomon (RS-16) encoder used on many NASA missions (XTE, TRMM, MAPS, and FUSE) Replace the Pegasus serial interface with the PLASMAG serial interface Modify RAD6000 processor to accommodate 7 Mbytes SRAM: C&DH / EPIC flight software requires additional processor memory for new tasks Make a minor design modification and new layout on the BMS to accommodate new DRAM modules Replace the obsolete Irvine Sensor DRAM modules used on previous SMEX missions with the tested Dense Pack DRAM modules being developed for NRL-NEMO program Triana SDR June 7 - 9, 1999

3 Computation Hub Changes from SMEX-LITE Design (Cont.)
Replace the +5VActel FPGA PCI target with the new +3.3V ASIC PCI target : The RAD6000 PCI ASIC initiator (LIO) requires the 3.3V power to improve the reliability The +3.3V ASIC PCI target being developed is functionally compatible with the existing SMEX ACTEL PCI target and is electrically compatible with LIO ASIC PCI initiator Redesign the backplane to support +3.3V PCI interface Use the tested SMEX-lite/Solstice LVPC design to provide additional 3.3V power buses on the backplane Triana SDR June 7 - 9, 1999

4 Computation Hub Implementation
Make necessary changes to existing SMEX-LITE Computation Hub design for Triana requirements Use EEE parts from SMEX-LITE inventory Provide technical support to Triana instrument design teams GFE flight boards and subsystems to Triana instrument teams: LM - EPIC Computer Hub Flight RAD 6000 Flight Memory and 1553 Summit card Flight EPIC Camera Interface card Flight LVPC Flight backplane Flight enclosure PCI ASIC target and user interface design Computation Hub documentation Spacecraft simulator for software/hardware development Ball - NISTAR Triana SDR June 7 - 9, 1999

5 Computation Hub Functional Capabilities
LMF RAD bit Processor Card Uses SMEX-Lite/VCL RAD 6000 version with 7 Mbytes RAD Hard SRAM Hosts flight software (C&DH, ACS, spacecraft safehold, and Power Control) Provides PCI bus master data transferring between cards through PCI backplane Provides direct Instrument data transfer through high speed serial interfaces Communication Interface Card Supports CCSDS Command and Telemetry standards Hardware generated fill-frame construction minimizes the processor burden Supports selectable downlink encoding options including Reed-Solomon Generates MET, watchdogs, PLASMAG serial interface and 3 UARTS Memory & 1553 Summit Card 320 Mbytes DRAM baseline implementation with onboard EDAC capability 1 Mbytes EEPROM for normal mode use 1553 B interface with use of UTMC 1553 Summit chip PCI backplane Allows DMA and other transfers between cards Four cards plus backplane Triana SDR June 7 - 9, 1999

6 TRIANA COMPUTATION HUB TOP LEVEL BLOCK
SUROM OSC Main Memory RAD6000 Local I/O Interfaces RS232 Hardware Test IF Timer/Time-Out Intr/Discretes PCI Local Bus High Speed Serial IF JTAG 320 Mbytes DRAM 1 Mbytes EEPROM 1553B +5V & 3.3V ONLY TRIANA PROCESSOR Downlink I/F Uplink I/F HW CMD To Mag_Plasma UARTS 1 1553 B 1553 A 1553b BUS Communication I/F card Memory & 1553 Sum card Uplink Downlink MET LVPC UART Lockheed Martin Design ( one card) SMEX Designs ( three cards) EPIC computer Triana SDR June 7 - 9, 1999

7 TRIANA COMPUTATION HUB FUNCTIONAL REQUIREMENTS (1)
Transponder interface for telemetry and command links CCSDS COP-1 uplink command decoding 2 Kbps CCSDS downlink telemetry encoding Hardware generation of CCSDS telemetry fill frames Spacecraft clock, time distribution, and synchronization EPIC Science data collection over high speed serial interface 5 Mbps (max.) data rate RS-422 electrical interface Bulk telemetry data storage with EDAC 256 Mbytes science data + 64 Mbytes EDAC = 320 Mbytes total Triana SDR June 7 - 9, 1999

8 TRIANA COMPUTATION HUB FUNCTIONAL REQUIREMENTS (2)
PLASMAG UART serial interface Receive telemetry data from Triana PLASMAG Instrument Send command data to Triana PLASMAG Instrument RS-422 electrical interface 1553 Bus Controller interface Command distribution Housekeeping data collection Processor & UART interfaces Watchdog & Power strobe interfaces: PCI reset (triggered by hardware watchdog, Barker watchdog) Power strobing (triggered by ground hardware command ) Host Flight Software C&DH, ACS, Power Control & Safehold PCI bus Interface Triana SDR June 7 - 9, 1999

9 TRIANA COMPUTATION HUB TOP LEVEL BLOCK
SUROM OSC Main Memory RAD6000 Local I/O Interfaces RS232 Hardware Test IF Timer/Time-Out Intr/Discretes PCI Local Bus High Speed Serial IF JTAG 320 Mbytes DRAM 1 Mbytes EEPROM 1553B +5V & 3.3V ONLY TRIANA PROCESSOR Downlink I/F Uplink I/F HW CMD PLASMAG TLM/CMD UART 1553 B 1553 A 1553b BUS EPIC computer Communication I/F card Memory & 1553 Sum card Uplink Downlink MET UARTS LVPC Lockheed Martin Design ( one card) SMEX Designs ( three cards) Triana SDR June 7 - 9, 1999

10 FLIGHT PROCESSOR CARD Side A: Side B: S/N 001 Triana SDR
June 7 - 9, 1999

11 TRIANA FLIGHT PROCESSOR TOP LEVEL BLOCK
Main Memory 7 Mbytes RHSRAM Pipeline Control Unit RAD6000 EEPROM 1 Mbytes Fixed Point Unit I/O Sequencer Unit Floating Point Unit Fetch/Instruction Buff Unit Cache Unit (8K) SUROM 64Kbytes Memory Interface Unit w/ EDAC Address Translation Unit 20 Mhz OSC SUROM Control Function LIO Timer/Time-Out Interrupt Collection & Reporting Function Local Memory Address & Control Function Intr/Discretes UART-RS422 H/W Test IF UART Interface Function Interrupts/Discretes Function JTAG Master Function Proc Avail Seq Function Clocks & Timers Function High Speed Serial IF(QHSS) RS-422 Chip Test/Diags Functions Reset Control PCI Bridge Function PCI Master/Central Arbiter +5V DC JTAG +3.3 V DC Computation Hub Backplane PCI Local Bus Triana SDR June 7 - 9, 1999

12 Flight Processor Card (1)
PCI Industry Standard Interface Any qualified PCI component will interface to TRIANA Comp-Hub Future upgrade path to any PCI Master processor w/out ripple through system interfaces Delivers RAD-hard performance needed to accommodate additional software requirements Boot mode safehold, power control Processor hardware debug environment available off-the-shelf RISCwatch, JTAG, VMETRO PCI Bus Analyzers Real Time Multi-tasking Kernel support VxWorks Operating System Triana SDR June 7 - 9, 1999

13 Flight Processor Card (2)
Memory Interface Unit handles accesses to/from local memory and provides RAM data to the Cache Unit Cache Unit coordinates accesses to the Cache Instruction Buffer Unit pulls instructions from the cache and dispatches instructions to the fixed point, floating point, and in-page fetcher (branch instructions) Fixed Point Unit provide pipelined execution for fixed point instructions I/O Sequencer Interfaces to RSC I/O bus and provides for initialization of the processor at startup Pipeline Control Unit Controls sequencing and interlocking operation of other functional units COP (Chip On Processor) Unit Interfaces with external test equipment and assists in the resetting and initialization of the processor registers and arrays Triana SDR June 7 - 9, 1999

14 Flight Processor Card (3)
RAD bit RISC Super Scalar Single Chip 22 20 MHz 7 Mbytes RHSRAM 1 Mbytes EEPROM 64 Kbytes SUROM Programmable Processor/PCI clocks: 20, 10, 5 or 2.5 MHZ 10 External Programmable Interrupts via LIO 8 RAD6000 level interrupts Peripheral Component Interconnect(PCI) Bus Full Mastership Local to PCI I/O Space DMA capable 16 Mbytes/sec Bus Transfers Four High Speed Serial Interfaces 5 Mbps per each Full Duplex (RS-422 electrically) DMA capable UART Interface (RS-422) 20 MHz < 7 W +5.0 VDC, +3.3 VDC Triana SDR June 7 - 9, 1999

15 Flight Processor Card (4)
Board Radiation Characteristics Total Dose : 50K rads(Si) (Hitachi 128Kx8 EEPROM in Austin Semi. package) Latch-up Immune Upset rate: GCR: per 5-year mission Solar Flares: 1.0 per 5 year mission (5 flares in a day) SEU (LET): >80 Mev/mg/cm**2 Physical 7.07 in. X 7.3 in. 1.989 pounds or .904 kgs 11 SMEX-Lite RAD6000 processor boards built and delivered: 3 for Triana 4 for EOS-Solstice 2 for VCL 2 for SMEX-Lite VxWorks Operating System Host Flight Software Triana SDR June 7 - 9, 1999

16 TRIANA COMPUTATION HUB TOP LEVEL BLOCK
6/6/96 SUROM OSC Main Memory RAD6000 Local I/O Interfaces UART-RS422 Hardware Test IF Timer/Time-Out Intr/Discretes PCI Local Bus High Speed Serial IF JTAG Uplink Downlink MET UARTS 320 Mbytes DRAM 1 Mbytes EEPROM 1553B +5V & 3.3V ONLY SMEX Designs ( three cards) Lockheed Martin Design ( one card) TRIANA PROCESSOR Downlink I/F Uplink I/F HW CMD To PLASMAG UART 1553 B 1553 A 1553b BUS Memory & 1553 Sum card Communication I/F card LVPC EPIC computer Triana SDR June 7 - 9, 1999

17 PCI Target Interface Implementation
PCI target core purchased PCI Bus interface implemented and tested with +5V FPGA in the SMEX_lite Comp-Hub Modified user interface to support specific peripheral component interfaces PCI target core implemented in LMFS RAD HARD ASIC Core Simulated per PCI Specification Rev 2.0 Single Configuration Reads/Writes Single and Burst Memory Reads/Writes Triana SDR June 7 - 9, 1999

18 COMMUNICATION INTERFACE CARD IMPLEMENTATION
Uplink 2 Kbps uplink interface, H/W command decoder Downlink Programmable downlink rate range: 4 M bps-300 bps Programmable 32 modulation index levels Hardware fill frame generator Coding options (Reed Solomon, Convolutional, PN and/or Bi-phase L encoding) Timers Hardware watchdog, Mission Elapsed Time PLASMAG UART Serial Interface External Interfaces 1 UART (RS-422 electrically) PCI Slave interface Triana SDR June 7 - 9, 1999

19 COMMUNICATION INTERFACE CARD
Side A Side B Triana SDR June 7 - 9, 1999

20 COMMUNICATION INTERFACE TOP-LEVEL BLOCK DIAGRAM
16 MHZ HW CMD DECODER 16 MHZ 8 MHZ CMD IF UP_DAT 8 UP CONTROLLER UP_FIFO UP_WR TO BACKPLANE DN_DAT 32 DOWN CONTROLLER DN_WR 8X4KX9 DN_FIFO TELEMETRY OUT To Transponder 3 FPGAs Hardline to GSE RS RS422 LOC_DATA PCI_TARGET HW WATCHDOG PULSE 8 MHZ MET 1 HZ RD,WR,FLAG_STAT PM_DAT_IN 8 PM_FIFO 4 k x9 UDATA UART IF 8 8 LOC_ADDRESS PLASMAG_SERIAL PM_UART ASIC MET_UARTS CONTROLLER UART_SEL, CNTRL SER_CHANNEL UART FPGA FPGA Triana SDR June 7 - 9, 1999

21 TRIANA COMPUTATION HUB TOP
LEVEL BLOCK SUROM OSC Main Memory RAD6000 Local I/O Interfaces RS232 Hardware Test IF Timer/Time-Out Intr/Discretes PCI Local Bus High Speed Serial IF JTAG 320 Mbytes DRAM 1 Mbytes EEPROM 1553B +5V & 3.3V ONLY SMEX Designs ( three cards) Lockheed Martin Design ( one card) TRIANA PROCESSOR Downlink I/F Uplink I/F HW CMD To PLASMAG UART 1553 B 1553 A 1553b BUS Communication I/F card Memory & 1553 Sum card Uplink Downlink MET UARTS LVPC 6/6/96 Triana SDR June 7 - 9, 1999

22 MEMORY & 1553 SUMMIT CARD DRAM Bulk Memory EEPROM Memory
320 Mbytes of data storage using Mx8 bit DRAM modules (Dense-pac DPD32MX8RG5-06C): Organized into Mbyte banks DRAM module consists of 4 64M bit Samsung DRAM (KM48C8000AS-6, 5.0V, REV A) chips stacked in a module by Dense-Pac EDAC with single & multi bit error interrupts DRAM Refresh Controller EEPROM Memory 1Mbytes of normal mode code storage Use 8 128Kx8 Hitachi CMOS EEPROM dies packaged by Austin Semiconductor On-orbit programmable 1553 Bus Controller Interface PCI Slave Interface Triana SDR June 7 - 9, 1999

23 MEMORY & 1553 SUMMIT CARD Side A Side B Triana SDR June 7 - 9, 1999

24 MEMORY&1553 SUMMIT TOP-LEVEL BLOCK DIAGRAM
32 DRDATA DRAM MODULES (10 X 32M X 8 BITS) DRADDR 12 8 DRCKBITS DRAM/EDAC CONTROLLER TO BACKPLANE EEPROM 1 EEPROM 5 LOC_DATA 32 FPGA EEPROM 4 EEPROM 8 PCI_TARGET 1 M BYTES EEPROM DAT CHANNEL A 1553 SUMMIT ADDR LOC_ADDRESS CHANNEL B EEPROM_SUM CONTROLLER ASIC SHARED RAM 64K x 16 24 MHZ FPGA 48 MHZ Triana SDR June 7 - 9, 1999

25 TRIANA COMPUTATION HUB TOP LEVEL BLOCK
6/6/96 SUROM OSC Main Memory RAD6000 Local I/O Interfaces RS232 Hardware Test IF Timer/Time-Out Intr/Discretes PCI Local Bus High Speed Serial IF JTAG 320 Mbytes DRAM 1 Mbytes EEPROM 1553B +5V & 3.3V ONLY SMEX Designs ( three cards) Lockheed Martin Design ( one card) TRIANA PROCESSOR Downlink I/F Uplink I/F HW CMD UART 1553 B 1553 A 1553b BUS Communication I/F card Memory & 1553 Sum card Uplink Downlink MET UARTS LVPC To PLASMAG Triana SDR June 7 - 9, 1999

26 Low Voltage Power Converter
LVPC: Uses SMEX-Lite/Solstice LVPC version Uses the COTS Interpoint EMI filter and DC-to-DC converters Complies 461 EMI specification Converts +28V input to +5V and +3.3V outputs Provides +5V to Communication I/F, Memory & 1553 Summit, Processor, & Backplane terminations Provides +3.3V to Flight Processor and PCI target ASICs Generates PCI Reset (POR 0) signal Triana SDR June 7 - 9, 1999

27 Low Voltage Power Converter
Triana SDR June 7 - 9, 1999

28 LVPC FUNCTIONAL BLOCK DIAGRAM
+3.3V LINE +28 V +28 V_C POWER CONNECTOR EMI FILTER +28 V RTN DC-TO-DC +3.3 V +28 V RTN_C TLM_3.3V +5.0V LINE TLM_5V TLM_IF PCI_ BACKPLANE I/F DC-TO-DC +5.0 V THERM_3.3V THERM_5V THERM_IF SIGNAL CONNECTOR INHIBIT ON SW_RST OPTO- ISOLATED RESET I/F RST# RESET_A CONTROL LOGIC RESET_B SW_RST Triana SDR June 7 - 9, 1999

29 Computation Hub Backplane
Support PCI Interface Signals (48) Pull-up resistors Support discrete signals Interrupts(4) Reset Distribute Power +5.0V DC at 8 Amp. (max.) DRAM/1553B/EEPROM Communications Interface Flight Processor +3.3V DC at 3 Amp. (max.) Flight Processor ASICs 2 PCI target ASICs CompHub Backplane +5.0 V & +3.3 V Power PCI Bus Signal Interface Interrupts(4) & HW Reset Low Voltage Power Converter RAD6000 Processor DRAM/1553/EEPROM card Communication Interface card Triana SDR June 7 - 9, 1999

30 Computation Hub Enclosure Implementation
SMEX.Lite Computation Hub: Houses all Comp Hub cards Card size (inches): 7.0 x 7.3 Box dimension (inches): 5 W x 7.5 H x 8.2 D Total weight: 12.25 lbs measured/estimated Triana SDR June 7 - 9, 1999


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