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.1 1999 ©UCB CS 161Computer Architecture Chapter 5 Lecture 9 Instructor: L.N. Bhuyan Adapted from notes by Dave Patterson (http.cs.berkeley.edu/~patterson)

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Presentation on theme: ".1 1999 ©UCB CS 161Computer Architecture Chapter 5 Lecture 9 Instructor: L.N. Bhuyan Adapted from notes by Dave Patterson (http.cs.berkeley.edu/~patterson)"— Presentation transcript:

1 ©UCB CS 161Computer Architecture Chapter 5 Lecture 9 Instructor: L.N. Bhuyan Adapted from notes by Dave Patterson (http.cs.berkeley.edu/~patterson)

2 ©UCB Where We Are: Machine Organization Personal Computer Processor (CPU) Computer Control (“brain”) Datapath (“brawn”) Memory Devices Input Output Arithmetic- Logic Unit (ALU) Chap. 7 (done) Chap. 8 Processor = Chaps. 5 NOW Chap 5 : 2 weeks Chap 6 : 1 week Chap 7 : 3 weeks

3 ©UCB MIPS-lite processor °Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”) just enough to illustrate key ideas instruction set subset (3 groups): -arithmetic-logical: add, sub, and, or, slt -memory reference: lw, sw -control flow: j, beq -can we write real programs with just these? °Need up to 5 steps to execute any instruction in our subset: Step 1: fetch instruction Step 2-5: ?

4 ©UCB Instruction Execution Steps Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory operation Write Back 1. Read IM[PC] 2. Instruction Decode, PC = PC + 4, Register read 3.ALU operation, Branch address computation 4.LW/STORE in Data memory 5.Register Write

5 ©UCB building a Datapath for MIPS (step 1) PC Memory Step 1. add $t0,$t0,$t0 add $t0,$s1,$t0 lw $t1,20($s0) sw $t1,4($t0). PC-4 PC PC+4 PC+8. Flow of execution °Need up to 5 steps to execute any instruction: Step 1: fetch instruction

6 ©UCB Datapath Step 1: any instruction PC Imem Read Address Instruction AddAdd “4” 32-bit adder or ALU wired only for add Clock Once program is loaded, Imem is read-only

7 ©UCB building a Datapath for MIPS (step 2) PCRegisters Step 1Step 2: Decode and Read Registers add $t0,$s1,$t0 Memory (instruc- tion) op rs rt rd shamt funct R

8 ©UCB Datapath Step 2: any instruction Register File Read Register 1 Read data 1 Read data 2 Read Register 2 Write Register Write Data Instruction Control Datapath Control Points RegWrite (“write enable” control point) 6 op rs rt rd shamt funct R add $t0,$t1,$t2

9 ©UCB Up to 5 Steps in Executing MIPS Subset °3rd step onwards depends on instruction class °EX: for ALU instructions, add $t0, $t1, $t2 outputs from registers t1 and t2 will be sent to the ALU input. °For Memory-reference instruction: A ddress  Base + offset lw$t0,20($s0) ALUALU

10 ©UCB building a Datapath for MIPS ( lw step 3) PCRegisters ALUALU Memory (instruc- tion) Step 1Step 2Step 3 op rs rt address lw $t0, 20($s0) I

11 ©UCB Datapath Step 3-4: R-format Instructions Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruction Result Zero ALU control 3 32 RegWrite add, sub, and, or, slt [$t1] [$t2] [$t2] { +, -, AND, OR, etc.}

12 ©UCB Datapath Step 3: Branch Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruc- tion Zero RegWrite Sign Extend AddAdd Branch target To branch control logic PC + 4 from step 1 datapath Mult by 4 beq $t0,$t1,loop ALU control 3 Result [$t0] [$t1]

13 ©UCB Datapath Step 3: Branch Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruc- tion Zero RegWrite Sign Extend AddAdd Branch target To branch control logic PC + 4 from step 1 datapath Mult by 4 beq $t0,$t1,loop ALU control 3 Result [$t0] [$t1]

14 ©UCB building a Datapath for MIPS ( lw step 4) PCRegisters ALUALU Step 1Step 2Step 3.. add $t0,$t0,$t0 add $t0,$s1,$t0 lw $t1,20($s0) sw $t1,4($t0). Memory (data) Step 4 Memory (instruc- tion)

15 ©UCB Up to 5 Steps in Executing MIPS Subset °4th step depends on instruction class Ex: for lw : Fetch Data from Memory Data  Mem[Address] For sw: Put the contents of a register in Memory Memory (data) ALUALU From Register for SW To register for LW

16 ©UCB Up to 5 Steps in Executing MIPS Subset °5th step only for lw ; rest are done EX: for lw : Write Result Reg[rt]  Data Memory (data) Registers ALUALU

17 ©UCB Datapath Step 3-5: Load/Store Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruc- tion Zero ALU control RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite lw $t0,24($s3) op rs rt address Result [$s3] “24” [$s3]+24

18 ©UCB Compose Datapath: R-form + Load/Store Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instr- uction Zero ALU control 3 RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite 1Mux01Mux0 MemTo- Reg 0=R-form 1=L/S MuxMux ALUSrc 0 = R-format 1 = Load/Store Add muxes


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