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**Multiplication Schemes Continued**

Lecture 7 Multiplication Schemes Continued

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**Multiplying by a constant**

Use binary expansion Example: multiply R 1 by 113 = ( )two R2 ¬ R1 shift-left 1 R3 ¬ R2 + R1 R6 ¬ R3 shift-left 1 R7 ¬ R6 + R1 R112 ¬ R7 shift-left 4 R113 ¬ R112 + R1 Only two registers are required; R1 and another Explicit multiplications, e.g. y : = 12 * x + 1

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**Multiplying by a constant**

Shorter sequence using shift-and-add instructions R3 ¬ R1 shift-left 1 + R1 R7 ¬ R3 shift-left 1 + R1 R113 ¬ R7 shift-left 4 + R1 (i.e. 7 * ) Use of factoring may help Example: multiply R1 by 119 = 7 * 17 = (8 – 1) * (16 + 1) R8 ¬ R1 shift-left 3 R7 ¬ R8 – R1 R112 ¬ R7 shift-left 4 R119 ¬ R112 + R7

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**Basic Multiplication Equations**

k-1 x = xi ri p = a x i=0 k-1 p = a x = xi ri = = x0ar0 + x1a r1 + x2a r2 + … + xk-1a rk-1 i=0

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**High-Radix Shift/Add Algorithms Right-shift high-radix algorithm**

p = a x = x0ar0 + x1ar1 + x2ar2 + … + xk-1ark-1 = = (...((0 + x0ark)/r + x1ark)/r xk-1ark)/r = k times p(0) = 0 p(j+1) = (p(j) + xj a rk) / r j=0..k-1 p = p(k)

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**Radix 4, or 2 bit at a time multiplication in dot notation**

This needs to be formed and added to cumulative partial product Shifted by two spaces Need to multiply the multiplicand by either 0, 1, 2 or 3. i.e. 0a, 1a, 2a or 3a. 2a is nothing but a shift; 3a can be computed as (2a +1a). This can be computed at the outset.

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**The multiple generation part of a radix 4 multiplier with precomputation of 3a Fig 10.2**

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**Example of radix-4 multiplication using the 3a multiple. Fig 10.3**

Added to accommodate the shift by 4 at next step (2 * a) (3 * a)

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**Extending the computations to higher radices, 8, 16 etc**

The concepts of Fig 10.2 can be extended to radices 8, Etc. However the complexity increases and introduces delays that nullify any speed up gains. For example, in radix 8, 3a, 5a and 7a need to be computed at outset 1a, 2a, 4a, 6a (2a + 4a) can be computed easily

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The multiple generation part of a radix-4 multiplier based on replacing 3a and 4a (carry into the next higher radix-4 multiplier digit) and –a Fig 10.4 when 3a needs to be added: we add –a and send a carry of 1 into the next radix-4 digit of the multiplier

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Radix-4 multiplication with a carry-save adder used to combine the cumulative partial product, xia and 2xi+1a into two numbers. Figure 10.7 CSA helps in generating all the required multiples without reducing the add time. It can be argued that it can add slight increase in compute time due to overhead required by added circuit for 3a Selecting these two mux inputs generate 3a

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Radix-2 multiplication with the upper half of the cumulative partial product kept in stored-carry form. Fig 10-8 CSA and multiplexer in the radix-4 multiplier can be put to better use for reducing the addition time in radix-2 multiplication by keeping the cumulative partial product in stored-carry form. Only the upper half of the cumulative partial product needs to be kept in redundant form, since e add the three values that form the next cumulative partial product, one bit of the final product is obtained in standard binary form and is shifted into the lower half of the double-width partial product register. This eliminates the need for carry propagation in all but the final addition.

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Radix-4 multiplication, with the cumulative partial product, xia, and 2xi+1a combined into two numbers by two carry-save adders. Fig 10-11

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Radix-16 multiplication with the upper half of the cumulative partial product in carry-save form. Fig 10-12

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High-radix multipliers as intermediate between sequential radix-2 and full tree multipliers. Fig 10-13

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**Array Multipliers a4 a3 a2 a1 a0 * x4 x3 x2 x1 x0**

a4x0 a3x0 a2x0 a1x0 a0x0 a4x1 a3x1 a2x1 a1x1 a0x1 a4x2 a3x2 a2x2 a1x2 a0x2 a4x3 a3x3 a2x3 a1x3 a0x3 a4x4 a3x4 a2x4 a1x4 a0x4 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 The partial products generated in a 5x5 multiplication

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**A basic array multiplier uses a one-sided CSA tree and a ripple-carry adder. Fig. 11.10**

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**Details of a 5 ´ 5 array multiplier using FA blocks. Fig 11-11**

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**1) Design an 8x8 right shift sequential multiplier. **

Assignment 4: All design to be done in VHDL/Verilog + Synthesis. Reports to be generated for each design. List how fast each design can operated at. Due April 14 1) Design an 8x8 right shift sequential multiplier. 2) Design a 8x6 radix-4 multiplier (a) Using 3a multiple (b) Using concept of Figure 10.4 3) Design a 16x16 multiplier using Radix-16 multiplication as depicted in Fig 10-12 4) Design a 32x32 multiplier using array multiplier (Fig 11-11). Is this multiplier conducive to pipelining?

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UNIVERSITY OF MASSACHUSETTS Dept

UNIVERSITY OF MASSACHUSETTS Dept

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