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1 Lecture 7 Multiplication Schemes Continued

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2 Multiplying by a constant Use binary expansion Example: multiply R 1 by 113 = (1110001)two R 2 R 1 shift-left 1 R 3 R 2 + R 1 R 6 R 3 shift-left 1 R 7 R 6 + R 1 R 112 R 7 shift-left 4 R 113 R 112 + R 1 Only two registers are required; R 1 and another Explicit multiplications, e.g. y : = 12 * x + 1

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3 Multiplying by a constant Shorter sequence using shift-and-add instructions R3 R 1 shift-left 1 + R 1 R7 R 3 shift-left 1 + R 1 R 113 R 7 shift-left 4 + R 1 (i.e. 7 * 16 + 1) Use of factoring may help Example: multiply R 1 by 119 = 7 17 = (8 – 1) * (16 + 1) R 8 R 1 shift-left 3 R 7 R 8 – R 1 R 112 R 7 shift-left 4 R 119 R 112 + R 7

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4 Basic Multiplication Equations x = x i r i i=0 k-1 p = a x p = a x = x i r i = = x 0 ar 0 + x 1 a r 1 + x 2 a r 2 + … + x k-1 a r k-1 i=0 k-1

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5 High-Radix Shift/Add Algorithms Right-shift high-radix algorithm p = a x = x 0 ar 0 + x 1 ar 1 + x 2 ar 2 + … + x k-1 ar k-1 = (...((0 + x 0 ar k )/r + x 1 ar k )/r +... + x k-1 ar k )/r = k times = p (0) = 0 p = p (k) p (j+1) = (p (j) + x j a r k ) / r j=0..k-1

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6 Radix 4, or 2 bit at a time multiplication in dot notation This needs to be formed and added to cumulative partial product Shifted by two spaces Need to multiply the multiplicand by either 0, 1, 2 or 3. i.e. 0a, 1a, 2a or 3a. 2a is nothing but a shift; 3a can be computed as (2a +1a). This can be computed at the outset.

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7 The multiple generation part of a radix 4 multiplier with precomputation of 3a Fig 10.2

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8 Example of radix-4 multiplication using the 3a multiple. Fig 10.3 (2 * a) (3 * a) Added to accommodate the shift by 4 at next step

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9 Extending the computations to higher radices, 8, 16 etc The concepts of Fig 10.2 can be extended to radices 8, 16.. Etc. However the complexity increases and introduces delays that nullify any speed up gains. For example, in radix 8, –3a, 5a and 7a need to be computed at outset –1a, 2a, 4a, 6a (2a + 4a) can be computed easily

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10 The multiple generation part of a radix-4 multiplier based on replacing 3a and 4a (carry into the next higher radix-4 multiplier digit) and –a Fig 10.4 when 3a needs to be added: we add –a and send a carry of 1 into the next radix-4 digit of the multiplier

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11 Radix-4 multiplication with a carry-save adder used to combine the cumulative partial product, x i a and 2x i+1 a into two numbers. Figure 10.7 Selecting these two mux inputs generate 3a CSA helps in generating all the required multiples without reducing the add time. It can be argued that it can add slight increase in compute time due to overhead required by added circuit for 3a

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12 Radix-2 multiplication with the upper half of the cumulative partial product kept in stored- carry form. Fig 10-8 CSA and multiplexer in the radix-4 multiplier can be put to better use for reducing the addition time in radix-2 multiplication by keeping the cumulative partial product in stored-carry form. Only the upper half of the cumulative partial product needs to be kept in redundant form, since e add the three values that form the next cumulative partial product, one bit of the final product is obtained in standard binary form and is shifted into the lower half of the double-width partial product register. This eliminates the need for carry propagation in all but the final addition.

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13 Radix-4 multiplication, with the cumulative partial product, x i a, and 2x i+1 a combined into two numbers by two carry-save adders. Fig 10-11

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14 Radix-16 multiplication with the upper half of the cumulative partial product in carry-save form. Fig 10-12

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15 High-radix multipliers as intermediate between sequential radix-2 and full tree multipliers. Fig 10-13

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16 Array Multipliers a4a3a2a1a0 *x4x3x2x1x0 a4x0a3x0a2x0a1x0a0x0 a4x1a3x1a2x1a1x1a0x1 a4x2a3x2a2x2a1x2a0x2 a4x3a3x3a2x3a1x3a0x3 a4x4a3x4a2x4a1x4a0x4 P9P8P7P6P5P4P3P2P1P0 The partial products generated in a 5x5 multiplication

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17 A basic array multiplier uses a one-sided CSA tree and a ripple-carry adder. Fig. 11.10

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18 Details of a 5 5 array multiplier using FA blocks. Fig 11-11

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19 Assignment 4: All design to be done in VHDL/Verilog + Synthesis. Reports to be generated for each design. List how fast each design can operated at. Due April 14 1) Design an 8x8 right shift sequential multiplier. 2) Design a 8x6 radix-4 multiplier –(a) Using 3a multiple –(b) Using concept of Figure 10.4 3) Design a 16x16 multiplier using Radix-16 multiplication as depicted in Fig 10-12 4) Design a 32x32 multiplier using array multiplier (Fig 11-11). Is this multiplier conducive to pipelining?

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