2 Jump & Subroutine Calls INSTRUCTION SETData HandlingArithmeticLogicData TestBranchJump & Subroutine CallsMost instructions are standard 68xx, but some new/efficient opcodes have been addedCourse structure and schedule does NOT support a back-to-the-basic instruction set presentation without cutting into other course material.Concentrate on helping attendees learn the instruction DETAILS(if necessary) during lab & exercises sessions instead of using class lecture time.DATA HANDLING: LOADS, STORES, PULLS, PUSH, TRANDFERS, INC, DEC, ROTATES, SHIFTSARITHMETIC: ADD, SUB, MULTLOGIC: AND, OR, EORDATA TEST: BIT TEST, COMPAREBRANCH: CONDITIONAL BRANCHES, BNE, BHIJUMP AND BRANCH JMP, JSRCONDITION CODE CLEARING OR SETTING BITSREFERENCES: A8ADI pg 10-4RM section 6 and Appendix A
4 DATA HANDLING INSTRUCTIONS (DATA MOVEMENT) FUNCTIONMNEMONICOPERATIONSTAAA (M)STORE ACMLTRSTABB (M)STDSTORE 16 BIT REGR (M)STXHR (M+1)STYLSTSPUSH DATAPSHA(SP) SP( REG) MTO STACKPSHBPSHC(SP)PSHDPSHXPSHY(SP) SP(R : R ) (M ):(M )HL(SP)(SP+1)PULAPULL DATA(M ) REG(SP)FROM STACKPULBPULC(SP) SPIntroduce Store & Push Instructions:Are used to save the contents of one or more CPU regs. At the start of subroutine or just before serving an interrupt.Instructions on slide are all memory to register opsStore Accumulator(A,B,D) affects N,Z clears V and leaves C unaffectedStore index & stack pointer --> CCR unaffectedPUSH’s --> CCR unaffectedFOR PUSH’s:Contents of ACCX are stored on the stack at the address contained in stack pointer, pointer is then decremented, Contents of ACCX do not changed.QUESTIONS:What type of addressing do we use with PHSA, etc ?????When would we want to use PSH and PUL???REFERENCES: A8ADI Section 10RM Appendix APULDPULXPULY(M ):(M ) R : R(SP) SP(SP)(SP)+1HLMOVE MOV MEM MEMEXAMPLE: MOVW 2,X+ , 2,-Y
5 STACK OPERATION EXAMPLE: PSHX PSHX MEM MEM SP SP SP SP XH XL BEFOREPSHXAFTERMEMMEMB7 B0B7 B0INCREASINGADDRESSESINCREASINGADDRESSESSP$3FFEXHXLTOP OF STACKSP$3FFFTOP OF STACKSP$4000SP$4000
6 DATA HANDLING INSTRUCTIONS (TRANSFER AND EXCHANGE) FUNCTIONMNEMONICOPERATIONTRANSFER DATATRANSFER REG TO REG TFR A, B, CCR, D, X, Y, SPA, B, CCR, D, X, Y, SPEXCHANGE EXG A, B, CCR, D, X, Y, SPTBAB ATABA BTXSR SPTYSTSYSP RTSXEXCHANGE DATAXGDXD XD YXGDYEXAMPLE1: TFR X ,AEXAMPLE2: EXG Y ,B
7 DATA HANDLING INSTRUCTIONS (ALTER DATA) FUNCTIONMNEMONICOPERATIONDECREMENTDEC(M) (M)DECAA ADECBB BDEXX XDEYY YDESS SINCREMENTINC(M) (M)INCAA AINCBB BIntroduce increment & decrement instructionsIncrement & decrement operations are available on ACCUM’s(A & B only)ACCUM A, B ops affect N,V & C only (no C)No 16-bit ACCD inc/dec is available (must use addd #1 etc)Index & stack pointer ops DO NOT affect CCRIncs/Decs are only direct manipulation of index regs/stack pointer- Subtract one from the contents of ACCX or M- Add one to the contents of ACCX or MINXX XINYY YINSS S
8 DATA HANDLING INSTRUCTIONS (ALTER DATA) FUNCTIONMNEMONICOPERATIONCOMPLEMENT, 2'SNEG0-(M) (M)(NEGATE)NEGA0-A ANEGB0-B BCOMPLEMENT, 1'SCOM(M) (M)COMAA ACOMBB BCLEARCLR(M)CLRAACLRBBINTRODUCE OTHER DATA HANDLING INSTRUCTIONS FOR ALTERING DATA.Emphasize efficiency of new BCLR & BSET insturctions:-NEG (2’s complement) affect N,Z,V,C- Replaces the contents of Accx or M with its 2’s complement “ THE VALUE $80 IS LEFT UNCHNAGED”-COM (1’s complement/invert all bits) affects only N,Z & clears V, sets C-Replace the contents of Accx or M with its 1’s complement-CLR (write 0’s to operand) clears N,V,C, and sets Z\- The contents of Accx or M are placed with 0’s-BSET, BCLR are used so SET/CLR memory operand bit(s) given by 1’s set in the instruction’s operand maskBCLR - clear multiple bits in location M. The bits to be cleard are specified by ones in the mask byteBSET - Set multiple bits in location M. The bits to be set are specified by 1’s in the mask byte-BSET, BCLR can ONLY use direct page or indexed addressing for the memory operand(significant restriction in practice)-BSET, BCLR affect N,Z, & clears V, & leaves C unaffected- Some assemblers use “BCLR <ea>,#mask” others use “BCLR <ea>mask”BIT(S) CLEARBCLR(M)MASK (M)BIT(S) SETBSET(M) +MASK (M)• Bit Manipulation Example: BSET OFFSET,X, #MASK
9 DATA HANDLING INSTRUCTIONS FUNCTIONMNEMONICOPERATIONMININUM OF TWOUNSIGNED 8-BITVALUEMINAMIN ((A), (M)) (A)MININUM OF TWOUNSIGNED 8-BITVALUEMINMMIN ((A), (M)) (M)MAXIMUM OF TWOUNSIGNED 8-BITVALUEMAXAMAX ((A), (M)) (A)MAXIMUM OF TWOUNSIGNED 8-BITVALUEMAXMMAX ((A), (M)) (M)LOOP MINA ,X+BHS LOOP
10 DATA HANDLING INSTRUCTIONS FUNCTIONMNEMONICOPERATIONMININUM OF TWOUNSIGNED 16-BITVALUEEMINDMIN ((D), (M:M+1)) (D)MININUM OF TWOUNSIGNED 16-BITVALUEMIN ((D), (M:M+1))M:M+1EMINMMAXIMUM OF TWOUNSIGNED 16-BITVALUEEMAXDMAX ((D), (M:M+1)) (D)MAXIMUM OF TWOUNSIGNED 8-BITVALUEEMAXMMAX ((D), (M:M+1))M:M+1
11 DATA HANDLING INSTRUCTIONS (SHIFT AND ROTATE) FUNCTIONMNEMONICOPERATIONROTATE LEFTROLMROLAAROLBBCb7b0ROTATE RIGHTRORMRORAARORBBCb7b0SHIFT LEFT,ASL(LSL)MARITHMETICASLA(LSLA)ACb7b0(LOGICAL)ASLB(LSLB)BASLD(LSLD)DABCb15b0SHIFT RIGHT,ASRMARITHMETICASRAAINTRODUCE SHIFT & ROTATE INSTRUCTIONS:ROL,ROR - rotate through carry bitROL(rotate left) - shifts all bits of Accx or M one place to the leftROR(rotate right) - shifts all bits of Accx or M one place to the rightNO 16-bit rotate for ACCDLSx, ASx, ROx all affect N,Z,V,CLSL & ASL are identical in operation & use same opcodeASL - Shifts all bits in Accx or M one place to the leftASR’s - Arithmetic shift rightsShift all of Accx or M one place to the right BIT 0 --> C & BIT 7 is held constantLEFT SHIFTS --> EFFICIENT WAY TO MULTIPLY BY POWERS OF 2RIGHT SHIFTS--> EFFICIENT WAY TO DIVIDE BY POWERS OF 2ASRBBb7b0CSHIFT RIGHT,LSRMLOGICALLSRAAb7b0CLSRBBLSRDDABb15b0C
12 DATA TEST INSTRUCTIONS FUNCTIONMNEMONICTESTBITAA (M)BIT TESTBITBB (M)COMPARECBAA-BCMPAA-(M)CMPBB-(M)CPDR -(M+1)LCPXRH-(M)-CCPYCOMPARE STACK CPS SP - ( M :M +1)TST(M)-0TEST, ZERO ORMINUSTSTAA-0TSTBB-0
13 CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3) MNEMONICCONDITIONCCR TESTINDICATION(L) BMIMINUSN=1r=NEGATIVE(L) BPLPLUSN=0r=POSITIVE*(L) BVSOVERFLOWV=1r=SIGN ERROR*(L) BVCNO OVERFLOWV=0r=SIGN OK*(L)BLTLESS[N V]=1A < M*(L)BGEGREATER OR EQUAL[N V]=0A >= M* (L)BLELESS OR EQUAL[Z+(N V)]=1A <= M*(L) BGTGREATER[Z+(N V)]=0A > MIndication(L)BEQEQUALZ=1A=Mrefers to theuse of a(L) BNECMPA MNOT EQUALZ=0A <> Minstructionimmediately(L)BHIHIGHER[C+Z]=0A > Mbefore thebranch(L) BLSLOWER OR SAME[C+Z]=1A <= M*Use for signedarithmetic only(L)BCC (BHS)CARRY CLEARC=0A >= M(L) BCS (BLO)CARRY SETC=1A < M
14 CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3) FUNCTIONMNEMONICOPERATIONDECREMENT & BRANCH DBEQ COUNTER - $ COUNTERIF COUNTER =0, THEN (PC)+$0003 +REL PCDBNE COUNTER - $01, COUNTERIF COUNTER <>0, THEN (PC)+$0003 +REL PCINCREMENT & BRANCH IBEQ COUNTER + $ COUNTERIF COUNTER =0, THEN (PC)+$0003 +REL PCIBNE COUNTER + $ COUNTERIF COUNTER <>0, THEN (PC)+$0003 +REL PCTBEQ IF COUNTER = 0, THEN PC+$ REL PCTBNE IF COUNTER <>0, THEN PC+$ REL PCTEST & BRANCHEXAMPLE:-LOOP MOVW $1000, 2,X+DBNE D,LOOP
15 BRANCH IF BITS SET OR CLEAR (3 of 3) • SINGLE INSTRUCTION TO LOGICALLY "AND" MASK WITH OPERAND ANDBRANCH IF BITS ARE EITHER SET OR CLEARED.• USEFUL FOR POLLING INTERRUPT STATUS FLAGS, AND FOR MAKING PROGRAMDECISIONS BASED ON BIT(S) VALUES.• BRANCH IS TAKEN FROM NEXT INSTRUCTION ADDRESS (OCL+4, 5, OR 6 )OP CODEOPERANDMASKBRANCH DISP.OCLBRSET(M) MASK SERVICEBRCLRA common misconception is that these instructions only work on direct addressing memeory space. NOT TRUE. By using indexed addressing they work anywhere in 64K, on any RAM, ROM, EEPROM or I/O or Control Registers.Please note that some care is needed in using BSET and BCLR instructions on I/O & control registers. It is easy to make mistakes because these intructions read the manipulated address and write a new value on a subsequent cycle of the instruction. For some I/O & Control registers, you are not reading and writing from the same place(it isn’t a RAM bit). Take the example of BSET instruction to set some bits in an I/O port before it is configured for outputs (by setting DDR bits). The read portion of the BSET instruction read the input levels at the pins while the write portion of the intruction writes data to the output pin latches(which are not yet connected to the pins). Since the read portion didn’t read the old state of the output pin latches, the new state written back to these latches later in the instruction doesn’t have anything to do with what used to be there. This was an inappropiate use of the bit manipulation instruction which could have been avoided by an understanding of how the instruction works and how the I/O port works.Users are tempted to use bit manipulation to clear timer system status flags. (Timer flags are cleared by writing a 1 to the flag after having read it while it was a 1). I you use BSET instruction you may clear more flags than intended because you would in fact clear any flag in the register that happened to be set during the operand read cycle of the BSET instruction, not just the bits that were set in the mask of the BSET instruction. You could use BCLR with a mask that has 0’s only in bits to be cleared. BCLR ANDs operand with the inverse of the mask.• ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX, IDX1 & IDX2.EXAMPLE:WAIT BRCLR PORTD,Y $80, WAIT
16 ARITHMETIC INSTRUCTIONS (4 of 4) FRACTIONAL DIVIDE INSTRUCTION FDIVRADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSBIF NUMERATOR IS GREATER THAN OR EQUAL TO THE DENOMINATOR,THEN V FLAG IS SET.RESULT EXAMPLES:A RESULT OF 1 IS 1/$10000 WHICH IS .0001A RESULT OF $C000 IS $C000/$10000 WHICH IS .75A RESULT OF $FFFF IS $FFFF/$10000 WHICH IS .9999
17 ARITHMETIC INSTRUCTIONS (1 of 4) FUNCTIONMNEMONICOPERATIONADDADDAA + (M) AADDBB + (M) BADDDD + (M+1) D ; D + M + C DLLHHADDABAA + B AACCUMULATORSABXX + B XABYY + B YADD WITH CARRYADCAA + M + C AINTRODUCE ADD & DECIMAL ADJUST INSTRUCTIONS:ABY - This is one of the rare places the Motorola instruction set isn’t entirely general.You can add B to X or Y but you can’t add A to X or Y. ABY is useful for calculating offsetts into multi-dimensional arrays.If you want to do 16-bit arithmetic on X or Y just do XGDX then 16-bit arithmetic such as ADDD, then XGDX again. Note X acts as temp for D in this seq.ABA & ADDs(A,B,D) affect N,Z,C,VABX & ABY (add ACCB to index register) does not affect CCRABX & ABY are useful for pointing index register to new (calculated) address (add ACCA to index register is not available)ADDC uses previous carry value as add-in carry in current additionDAA is only of use immediately AFTER executing ADDA, to transform the accumulator’s hexadecimal results to decimal using the Half carry bit.ADCBB + M + C BDECIMAL ADJUSTCONVERTS BINARY ADDITION OFDAABCD CHARS INTO BCD FORMAT
18 ARITHMETIC INSTRUCTIONS (2 of 4) FUNCTIONMNEMONICOPERATIONSUBTRACTSUBAA – (M)ASUBBB – (M) BSUBDD – (M+1) D ; D – (M) – C DLLHHSUBTRACTSBAA – B AACCUMULATORSA – (M) – C ASUBTRACT WITHSBCAB – (M) – C BCARRYSBCBINTRODUCE: SUBTRACT & MULTIPLY INSTRUCTIONSInstructions on slide are all register opsSBA & SUBs (A,B,D) affect N,Z,V,CSUBC uses previous carry value as a borrow in current subtractionMUL is 8x8 unsigned multiply giving a 16-bit resultMUL takes 10 clocks & affects C bit according to bit 7 (ACCB bit 7) of 16-bit resultQUESTION: WHAT DOES THE C BIT REPRESENT IN SUBTRACTION:MULTIPLY MUL A * B DEXTENDED MULTIPLY EMUL D * Y Y : DEXTENDED MULTIPLY EMULS D * Y Y : DSIGNED
19 ARITHMETIC INSTRUCTIONS (3 of 4) DIVIDE INSTRUCTIONS OPERATIOND REG / X REGRESULTQUOTIENT IS IN XREMAINDER IS IN DINTEGER DIVIDEIDIV/IDIVSRADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSBEXTENDED DIVIDE 32-BIT BY 16-BIT ( [UN ]SIGNED)EDIV/EDIVS-two DIV instructions are available, INTEGER & FRACTIONAL , both div’s use ACCD as dividend(numerator) and X as divisor(denominator), quotient is returned in X and remainder in ACCD.-IDIV returns integer quotient and integer remainder (value < divisor)-FDIV is intended for use when dividend < divisor (ie fractional result)If FDIV is succesful, then quotient (in X register) = 0 and remainder is 16 bit fractional value in ACCD.If FDIV fails (dividend > divisor) then quotient (in X register) = $FFFF and remainder is undefined.Condition codes: IDIV -Z =1 if quotient = 0 , C=1 if divisor = 0 FDIV-Z=1 if quotient =0 , V=1 if dividend >divisor, and C=1 if divisor =0IDIV (Unsigned Integer Divide) --> D / X --> Result = X, Remainder=DFDIV(Unsigned fractional divide) - it’s like multiplying the numerator by 2^^16 (left shift 16 times) and then doing a 32-Bit by 16-Bit integer divide.The result is interpreted as a weighted binary fraction which resulted from the division of a 16-bit integer by a larger 16-bit integer. The radix point(not decimal point that would imply base 10 and we are in base 2) is assumed to be immediately left of the MSB of the result. the remainder of the FDIV is an integer which , if divided by the original denominator(with another FDIV), will yield the next 16 bits further to the right of the radix point. This provides a way to extend the precision of the divide to any arbitrary number of places beyond the radix(though I don’t know why you would want to extend precision very far).Using The Divide Instructions:-Useful for A/D and D/A calculations: Result values can be compared to ratiometric A/D results, also results are in correct form to drive a weighted D/A-Good for % calculations: For example suppose you want to produce a waveform with a period of 6667 E-cycles and duty cycle of nn%.-FDIV may be executed after IDIV to resolve remainder: In fact FDIV can follow and FDIV to resolve more bits past radix.Ratiometric A/D and D/A values are also weighted binary fractions which express the analog value as a fractional portion of the analog reference. For example $C0 means 3/4 or 0.75(base 10) of the refence value. This idea also extends to percentage calculations. After all what is percentage but the result of dividing a number by 100?EDIV EXAMPLE: EDIV[ S ]OPERATION (Y:D)/ (X) Y; REMAINDER DV = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000C = 1, IF DIVISOR WAS $0000
20 EXTENDED MULTIPLY AND ACCUMULATE (EMACS) OPERATION: (M : M ) * (M : M ) + M ~ M+3) M ~ M+3(X) (X+1) (Y) (Y+1)XYEXAMPLE:EMACS $ (* 32-BIT RESULT *)
21 LOGIC INSTRUCTIONS FUNCTION MNEMONIC OPERATION AND ANDA A (M) A ANDB ANDCC CCR MASK CCRB (M) BEXCLUSIVE OREORAA (M) AEORBB (M) BINCLUSIVE ORORAAB + (M)BA + (M)AORABORCC CCR + MASK CCR
22 JUMP AND BRANCH INSTRUCTIONS FUNCTIONMNEMONICOPERATION/BRANCH TESTNO OPERATIONNOPPC ADVANCES TO NEXT INST.JUMP TO ADDRESSJMP(M) PC , (M+1) PCHLJUMP TO SUBROUTINEJSRPC (M ), SP SPLPC (M ), SP SPSPHSP(M) PC , (M+1) PCHLSP SP,(M ) PCSPHRETURN FROM SUBRTNRTSSP SP,(M ) PCSPLBSRPC (M ), SP SPBRANCH TO SUBRTNLSPPC (M ), SP SPHSP(M) PC , (M+1) PCHBRANCH ALWAYSBRANO TESTBRANCH NEVERBRNNO TEST, PC NEXT INST.
24 BLOCK MOVE ROUTINEWRITE A BLOCK MOVE ROUTINE. THE ROUTINE COPIES DATA FROM MEMORYLOCATION $5000 TO MEMORY LOCATION $5100. THE ROUTINE WILL END WHENA DATA BYTE WITH VALUE OF ZERO IS MOVED.WRITE YOUR PROGRAM HEREORG $5000SOURCE FCC ‘DATA TO MOVE’FCB 0ORG $4000LOOPBEQ DONEBRA LOOPDONE BRA DONESUGGESTED PROGRAM STEPSORIGINATE DATA AT ADDRESS $4000.FORM TABLE OF DATA TO BE MOVEDFORM CONSTANT BYTE OF ‘0’.PROGRAM1. INIT SOURCE POINTER T0 $5000.2. INIT DESTINATION POINTER TO $5100.3. GET DATA FROM SOURCE ADDRESS.4. WRITE DATA TO DESTINATION ADDRESS,5. IF DATA MOVED = 0, GO TO STEP 9,ELSE GO TO 6.6. INCREMENT SOURCE POINTER.7. INCREMENT DESTINATION POINTER.8. GO TO STEP 3.9. STAY HERE.
25 CLEAR RAM ROUTINEWrite a routine to clear the HCS12 RAM memory, assume RAM begins at $5000and ends at $5FFF.START LDX #$
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