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HCS12 Instruction set

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**Jump & Subroutine Calls**

INSTRUCTION SET Data Handling Arithmetic Logic Data Test Branch Jump & Subroutine Calls Most instructions are standard 68xx, but some new/efficient opcodes have been added Course structure and schedule does NOT support a back-to-the-basic instruction set presentation without cutting into other course material. Concentrate on helping attendees learn the instruction DETAILS(if necessary) during lab & exercises sessions instead of using class lecture time. DATA HANDLING: LOADS, STORES, PULLS, PUSH, TRANDFERS, INC, DEC, ROTATES, SHIFTS ARITHMETIC: ADD, SUB, MULT LOGIC: AND, OR, EOR DATA TEST: BIT TEST, COMPARE BRANCH: CONDITIONAL BRANCHES, BNE, BHI JUMP AND BRANCH JMP, JSR CONDITION CODE CLEARING OR SETTING BITS REFERENCES: A8ADI pg 10-4 RM section 6 and Appendix A

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**DATA HANDLING INSTRUCTIONS (DATA MOVEMENT)**

FUNCTION MNEMONIC OPERATION LOAD ACMLTR LDAA (M) A LDAB (M) B LDD (M) R LOAD 16 BIT REG LOAD <EA> LEAX <ea> X LEAY <ea> Y LEAS <ea> SP H LDX (M+1) R L LDY LDS Y B ACCB 2 5 Y 2000 MEM EXAMPLE: LEAX B,Y + X REG 2025

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**DATA HANDLING INSTRUCTIONS (DATA MOVEMENT)**

FUNCTION MNEMONIC OPERATION STAA A (M) STORE ACMLTR STAB B (M) STD STORE 16 BIT REG R (M) STX H R (M+1) STY L STS PUSH DATA PSHA (SP) SP ( REG) M TO STACK PSHB PSHC (SP) PSHD PSHX PSHY (SP) SP (R : R ) (M ):(M ) H L (SP) (SP+1) PULA PULL DATA (M ) REG (SP) FROM STACK PULB PULC (SP) SP Introduce Store & Push Instructions: Are used to save the contents of one or more CPU regs. At the start of subroutine or just before serving an interrupt. Instructions on slide are all memory to register ops Store Accumulator(A,B,D) affects N,Z clears V and leaves C unaffected Store index & stack pointer --> CCR unaffected PUSH’s --> CCR unaffected FOR PUSH’s: Contents of ACCX are stored on the stack at the address contained in stack pointer, pointer is then decremented, Contents of ACCX do not changed. QUESTIONS: What type of addressing do we use with PHSA, etc ????? When would we want to use PSH and PUL??? REFERENCES: A8ADI Section 10 RM Appendix A PULD PULX PULY (M ):(M ) R : R (SP) SP (SP) (SP)+1 H L MOVE MOV MEM MEM EXAMPLE: MOVW 2,X+ , 2,-Y

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**STACK OPERATION EXAMPLE: PSHX PSHX MEM MEM SP SP SP SP XH XL**

BEFORE PSHX AFTER MEM MEM B7 B0 B7 B0 INCREASING ADDRESSES INCREASING ADDRESSES SP $3FFE XH XL TOP OF STACK SP $3FFF TOP OF STACK SP $4000 SP $4000

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**DATA HANDLING INSTRUCTIONS (TRANSFER AND EXCHANGE)**

FUNCTION MNEMONIC OPERATION TRANSFER DATA TRANSFER REG TO REG TFR A, B, CCR, D, X, Y, SP A, B, CCR, D, X, Y, SP EXCHANGE EXG A, B, CCR, D, X, Y, SP TBA B A TAB A B TXS R SP TYS TSY SP R TSX EXCHANGE DATA XGDX D X D Y XGDY EXAMPLE1: TFR X ,A EXAMPLE2: EXG Y ,B

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**DATA HANDLING INSTRUCTIONS (ALTER DATA)**

FUNCTION MNEMONIC OPERATION DECREMENT DEC (M) (M) DECA A A DECB B B DEX X X DEY Y Y DES S S INCREMENT INC (M) (M) INCA A A INCB B B Introduce increment & decrement instructions Increment & decrement operations are available on ACCUM’s(A & B only) ACCUM A, B ops affect N,V & C only (no C) No 16-bit ACCD inc/dec is available (must use addd #1 etc) Index & stack pointer ops DO NOT affect CCR Incs/Decs are only direct manipulation of index regs/stack pointer - Subtract one from the contents of ACCX or M - Add one to the contents of ACCX or M INX X X INY Y Y INS S S

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**DATA HANDLING INSTRUCTIONS (ALTER DATA)**

FUNCTION MNEMONIC OPERATION COMPLEMENT, 2'S NEG 0-(M) (M) (NEGATE) NEGA 0-A A NEGB 0-B B COMPLEMENT, 1'S COM (M) (M) COMA A A COMB B B CLEAR CLR (M) CLRA A CLRB B INTRODUCE OTHER DATA HANDLING INSTRUCTIONS FOR ALTERING DATA. Emphasize efficiency of new BCLR & BSET insturctions: -NEG (2’s complement) affect N,Z,V,C - Replaces the contents of Accx or M with its 2’s complement “ THE VALUE $80 IS LEFT UNCHNAGED” -COM (1’s complement/invert all bits) affects only N,Z & clears V, sets C -Replace the contents of Accx or M with its 1’s complement -CLR (write 0’s to operand) clears N,V,C, and sets Z\ - The contents of Accx or M are placed with 0’s -BSET, BCLR are used so SET/CLR memory operand bit(s) given by 1’s set in the instruction’s operand mask BCLR - clear multiple bits in location M. The bits to be cleard are specified by ones in the mask byte BSET - Set multiple bits in location M. The bits to be set are specified by 1’s in the mask byte -BSET, BCLR can ONLY use direct page or indexed addressing for the memory operand(significant restriction in practice) -BSET, BCLR affect N,Z, & clears V, & leaves C unaffected - Some assemblers use “BCLR <ea>,#mask” others use “BCLR <ea>mask” BIT(S) CLEAR BCLR (M) MASK (M) BIT(S) SET BSET (M) + MASK (M) • Bit Manipulation Example: BSET OFFSET,X, #MASK

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**DATA HANDLING INSTRUCTIONS**

FUNCTION MNEMONIC OPERATION MININUM OF TWO UNSIGNED 8-BIT VALUE MINA MIN ((A), (M)) (A) MININUM OF TWO UNSIGNED 8-BIT VALUE MINM MIN ((A), (M)) (M) MAXIMUM OF TWO UNSIGNED 8-BIT VALUE MAXA MAX ((A), (M)) (A) MAXIMUM OF TWO UNSIGNED 8-BIT VALUE MAXM MAX ((A), (M)) (M) LOOP MINA ,X+ BHS LOOP

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**DATA HANDLING INSTRUCTIONS**

FUNCTION MNEMONIC OPERATION MININUM OF TWO UNSIGNED 16-BIT VALUE EMIND MIN ((D), (M:M+1)) (D) MININUM OF TWO UNSIGNED 16-BIT VALUE MIN ((D), (M:M+1)) M:M+1 EMINM MAXIMUM OF TWO UNSIGNED 16-BIT VALUE EMAXD MAX ((D), (M:M+1)) (D) MAXIMUM OF TWO UNSIGNED 8-BIT VALUE EMAXM MAX ((D), (M:M+1)) M:M+1

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**DATA HANDLING INSTRUCTIONS (SHIFT AND ROTATE)**

FUNCTION MNEMONIC OPERATION ROTATE LEFT ROL M ROLA A ROLB B C b7 b0 ROTATE RIGHT ROR M RORA A RORB B C b7 b0 SHIFT LEFT, ASL(LSL) M ARITHMETIC ASLA(LSLA) A C b7 b0 (LOGICAL) ASLB(LSLB) B ASLD(LSLD) D A B C b15 b0 SHIFT RIGHT, ASR M ARITHMETIC ASRA A INTRODUCE SHIFT & ROTATE INSTRUCTIONS: ROL,ROR - rotate through carry bit ROL(rotate left) - shifts all bits of Accx or M one place to the left ROR(rotate right) - shifts all bits of Accx or M one place to the right NO 16-bit rotate for ACCD LSx, ASx, ROx all affect N,Z,V,C LSL & ASL are identical in operation & use same opcode ASL - Shifts all bits in Accx or M one place to the left ASR’s - Arithmetic shift rights Shift all of Accx or M one place to the right BIT 0 --> C & BIT 7 is held constant LEFT SHIFTS --> EFFICIENT WAY TO MULTIPLY BY POWERS OF 2 RIGHT SHIFTS--> EFFICIENT WAY TO DIVIDE BY POWERS OF 2 ASRB B b7 b0 C SHIFT RIGHT, LSR M LOGICAL LSRA A b7 b0 C LSRB B LSRD D A B b15 b0 C

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**DATA TEST INSTRUCTIONS**

FUNCTION MNEMONIC TEST BITA A (M) BIT TEST BITB B (M) COMPARE CBA A-B CMPA A-(M) CMPB B-(M) CPD R -(M+1) L CPX R H -(M)-C CPY COMPARE STACK CPS SP - ( M :M +1) TST (M)-0 TEST, ZERO OR MINUS TSTA A-0 TSTB B-0

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**CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3)**

MNEMONIC CONDITION CCR TEST INDICATION (L) BMI MINUS N=1 r=NEGATIVE (L) BPL PLUS N=0 r=POSITIVE *(L) BVS OVERFLOW V=1 r=SIGN ERROR *(L) BVC NO OVERFLOW V=0 r=SIGN OK *(L)BLT LESS [N V]=1 A < M *(L)BGE GREATER OR EQUAL [N V]=0 A >= M * (L)BLE LESS OR EQUAL [Z+(N V)]=1 A <= M *(L) BGT GREATER [Z+(N V)]=0 A > M Indication (L)BEQ EQUAL Z=1 A=M refers to the use of a (L) BNE CMPA M NOT EQUAL Z=0 A <> M instruction immediately (L)BHI HIGHER [C+Z]=0 A > M before the branch (L) BLS LOWER OR SAME [C+Z]=1 A <= M *Use for signed arithmetic only (L)BCC (BHS) CARRY CLEAR C=0 A >= M (L) BCS (BLO) CARRY SET C=1 A < M

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**CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3)**

FUNCTION MNEMONIC OPERATION DECREMENT & BRANCH DBEQ COUNTER - $ COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC DBNE COUNTER - $01, COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC INCREMENT & BRANCH IBEQ COUNTER + $ COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC IBNE COUNTER + $ COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC TBEQ IF COUNTER = 0, THEN PC+$ REL PC TBNE IF COUNTER <>0, THEN PC+$ REL PC TEST & BRANCH EXAMPLE: - LOOP MOVW $1000, 2,X+ DBNE D,LOOP

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**BRANCH IF BITS SET OR CLEAR (3 of 3)**

• SINGLE INSTRUCTION TO LOGICALLY "AND" MASK WITH OPERAND AND BRANCH IF BITS ARE EITHER SET OR CLEARED. • USEFUL FOR POLLING INTERRUPT STATUS FLAGS, AND FOR MAKING PROGRAM DECISIONS BASED ON BIT(S) VALUES. • BRANCH IS TAKEN FROM NEXT INSTRUCTION ADDRESS (OCL+4, 5, OR 6 ) OP CODE OPERAND MASK BRANCH DISP. OCL BRSET (M) MASK SERVICE BRCLR A common misconception is that these instructions only work on direct addressing memeory space. NOT TRUE. By using indexed addressing they work anywhere in 64K, on any RAM, ROM, EEPROM or I/O or Control Registers. Please note that some care is needed in using BSET and BCLR instructions on I/O & control registers. It is easy to make mistakes because these intructions read the manipulated address and write a new value on a subsequent cycle of the instruction. For some I/O & Control registers, you are not reading and writing from the same place(it isn’t a RAM bit). Take the example of BSET instruction to set some bits in an I/O port before it is configured for outputs (by setting DDR bits). The read portion of the BSET instruction read the input levels at the pins while the write portion of the intruction writes data to the output pin latches(which are not yet connected to the pins). Since the read portion didn’t read the old state of the output pin latches, the new state written back to these latches later in the instruction doesn’t have anything to do with what used to be there. This was an inappropiate use of the bit manipulation instruction which could have been avoided by an understanding of how the instruction works and how the I/O port works. Users are tempted to use bit manipulation to clear timer system status flags. (Timer flags are cleared by writing a 1 to the flag after having read it while it was a 1). I you use BSET instruction you may clear more flags than intended because you would in fact clear any flag in the register that happened to be set during the operand read cycle of the BSET instruction, not just the bits that were set in the mask of the BSET instruction. You could use BCLR with a mask that has 0’s only in bits to be cleared. BCLR ANDs operand with the inverse of the mask. • ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX, IDX1 & IDX2. EXAMPLE: WAIT BRCLR PORTD,Y $80, WAIT

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**ARITHMETIC INSTRUCTIONS (4 of 4) FRACTIONAL DIVIDE INSTRUCTION**

FDIV RADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSB IF NUMERATOR IS GREATER THAN OR EQUAL TO THE DENOMINATOR, THEN V FLAG IS SET. RESULT EXAMPLES: A RESULT OF 1 IS 1/$10000 WHICH IS .0001 A RESULT OF $C000 IS $C000/$10000 WHICH IS .75 A RESULT OF $FFFF IS $FFFF/$10000 WHICH IS .9999

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**ARITHMETIC INSTRUCTIONS (1 of 4)**

FUNCTION MNEMONIC OPERATION ADD ADDA A + (M) A ADDB B + (M) B ADDD D + (M+1) D ; D + M + C D L L H H ADD ABA A + B A ACCUMULATORS ABX X + B X ABY Y + B Y ADD WITH CARRY ADCA A + M + C A INTRODUCE ADD & DECIMAL ADJUST INSTRUCTIONS: ABY - This is one of the rare places the Motorola instruction set isn’t entirely general. You can add B to X or Y but you can’t add A to X or Y. ABY is useful for calculating offsetts into multi-dimensional arrays. If you want to do 16-bit arithmetic on X or Y just do XGDX then 16-bit arithmetic such as ADDD, then XGDX again. Note X acts as temp for D in this seq. ABA & ADDs(A,B,D) affect N,Z,C,V ABX & ABY (add ACCB to index register) does not affect CCR ABX & ABY are useful for pointing index register to new (calculated) address (add ACCA to index register is not available) ADDC uses previous carry value as add-in carry in current addition DAA is only of use immediately AFTER executing ADDA, to transform the accumulator’s hexadecimal results to decimal using the Half carry bit. ADCB B + M + C B DECIMAL ADJUST CONVERTS BINARY ADDITION OF DAA BCD CHARS INTO BCD FORMAT

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**ARITHMETIC INSTRUCTIONS (2 of 4)**

FUNCTION MNEMONIC OPERATION SUBTRACT SUBA A – (M) A SUBB B – (M) B SUBD D – (M+1) D ; D – (M) – C D L L H H SUBTRACT SBA A – B A ACCUMULATORS A – (M) – C A SUBTRACT WITH SBCA B – (M) – C B CARRY SBCB INTRODUCE: SUBTRACT & MULTIPLY INSTRUCTIONS Instructions on slide are all register ops SBA & SUBs (A,B,D) affect N,Z,V,C SUBC uses previous carry value as a borrow in current subtraction MUL is 8x8 unsigned multiply giving a 16-bit result MUL takes 10 clocks & affects C bit according to bit 7 (ACCB bit 7) of 16-bit result QUESTION: WHAT DOES THE C BIT REPRESENT IN SUBTRACTION: MULTIPLY MUL A * B D EXTENDED MULTIPLY EMUL D * Y Y : D EXTENDED MULTIPLY EMULS D * Y Y : D SIGNED

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**ARITHMETIC INSTRUCTIONS (3 of 4) DIVIDE INSTRUCTIONS**

OPERATION D REG / X REG RESULT QUOTIENT IS IN X REMAINDER IS IN D INTEGER DIVIDE IDIV/IDIVS RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB EXTENDED DIVIDE 32-BIT BY 16-BIT ( [UN ]SIGNED) EDIV/EDIVS -two DIV instructions are available, INTEGER & FRACTIONAL , both div’s use ACCD as dividend(numerator) and X as divisor(denominator), quotient is returned in X and remainder in ACCD. -IDIV returns integer quotient and integer remainder (value < divisor) -FDIV is intended for use when dividend < divisor (ie fractional result) If FDIV is succesful, then quotient (in X register) = 0 and remainder is 16 bit fractional value in ACCD. If FDIV fails (dividend > divisor) then quotient (in X register) = $FFFF and remainder is undefined. Condition codes: IDIV -Z =1 if quotient = 0 , C=1 if divisor = 0 FDIV-Z=1 if quotient =0 , V=1 if dividend >divisor, and C=1 if divisor =0 IDIV (Unsigned Integer Divide) --> D / X --> Result = X, Remainder=D FDIV(Unsigned fractional divide) - it’s like multiplying the numerator by 2^^16 (left shift 16 times) and then doing a 32-Bit by 16-Bit integer divide. The result is interpreted as a weighted binary fraction which resulted from the division of a 16-bit integer by a larger 16-bit integer. The radix point(not decimal point that would imply base 10 and we are in base 2) is assumed to be immediately left of the MSB of the result. the remainder of the FDIV is an integer which , if divided by the original denominator(with another FDIV), will yield the next 16 bits further to the right of the radix point. This provides a way to extend the precision of the divide to any arbitrary number of places beyond the radix(though I don’t know why you would want to extend precision very far). Using The Divide Instructions: -Useful for A/D and D/A calculations: Result values can be compared to ratiometric A/D results, also results are in correct form to drive a weighted D/A -Good for % calculations: For example suppose you want to produce a waveform with a period of 6667 E-cycles and duty cycle of nn%. -FDIV may be executed after IDIV to resolve remainder: In fact FDIV can follow and FDIV to resolve more bits past radix. Ratiometric A/D and D/A values are also weighted binary fractions which express the analog value as a fractional portion of the analog reference. For example $C0 means 3/4 or 0.75(base 10) of the refence value. This idea also extends to percentage calculations. After all what is percentage but the result of dividing a number by 100? EDIV EXAMPLE: EDIV[ S ] OPERATION (Y:D)/ (X) Y; REMAINDER D V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000 V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000 C = 1, IF DIVISOR WAS $0000

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**EXTENDED MULTIPLY AND ACCUMULATE (EMACS)**

OPERATION: (M : M ) * (M : M ) + M ~ M+3) M ~ M+3 (X) (X+1) (Y) (Y+1) X Y EXAMPLE: EMACS $ (* 32-BIT RESULT *)

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**LOGIC INSTRUCTIONS FUNCTION MNEMONIC OPERATION AND ANDA A (M) A ANDB**

ANDCC CCR MASK CCR B (M) B EXCLUSIVE OR EORA A (M) A EORB B (M) B INCLUSIVE OR ORAA B + (M) B A + (M) A ORAB ORCC CCR + MASK CCR

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**JUMP AND BRANCH INSTRUCTIONS**

FUNCTION MNEMONIC OPERATION/BRANCH TEST NO OPERATION NOP PC ADVANCES TO NEXT INST. JUMP TO ADDRESS JMP (M) PC , (M+1) PC H L JUMP TO SUBROUTINE JSR PC (M ), SP SP L PC (M ), SP SP SP H SP (M) PC , (M+1) PC H L SP SP,(M ) PC SP H RETURN FROM SUBRTN RTS SP SP,(M ) PC SP L BSR PC (M ), SP SP BRANCH TO SUBRTN L SP PC (M ), SP SP H SP (M) PC , (M+1) PC H BRANCH ALWAYS BRA NO TEST BRANCH NEVER BRN NO TEST, PC NEXT INST.

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**CONDITION CODE REGISTER INSTRUCTIONS**

FUNCTION MNEMONIC OPERATION CLEAR CARRY CLC C CLEAR INTERRUPT MASK CLI I CLEAR OVERFLOW CLV V SET CARRY SEC C SET INTERRUPT MASK SEI I SET OVERFLOW SEV V ACCUMULATOR A CCR TAP A CCR CCR ACCUMULATOR A TPA CCR A OR CONDITION CODE ORCC CCR + OPERAND AND CONDITION CODE ANDCC CCR ^ OPERAND

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BLOCK MOVE ROUTINE WRITE A BLOCK MOVE ROUTINE. THE ROUTINE COPIES DATA FROM MEMORY LOCATION $5000 TO MEMORY LOCATION $5100. THE ROUTINE WILL END WHEN A DATA BYTE WITH VALUE OF ZERO IS MOVED. WRITE YOUR PROGRAM HERE ORG $5000 SOURCE FCC ‘DATA TO MOVE’ FCB 0 ORG $4000 LOOP BEQ DONE BRA LOOP DONE BRA DONE SUGGESTED PROGRAM STEPS ORIGINATE DATA AT ADDRESS $4000. FORM TABLE OF DATA TO BE MOVED FORM CONSTANT BYTE OF ‘0’. PROGRAM 1. INIT SOURCE POINTER T0 $5000. 2. INIT DESTINATION POINTER TO $5100. 3. GET DATA FROM SOURCE ADDRESS. 4. WRITE DATA TO DESTINATION ADDRESS, 5. IF DATA MOVED = 0, GO TO STEP 9, ELSE GO TO 6. 6. INCREMENT SOURCE POINTER. 7. INCREMENT DESTINATION POINTER. 8. GO TO STEP 3. 9. STAY HERE.

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CLEAR RAM ROUTINE Write a routine to clear the HCS12 RAM memory, assume RAM begins at $5000 and ends at $5FFF. START LDX #$

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