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ENG3640 Microcomputer Interfacing Week #3 Assembly Language Design and Structure.

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1 ENG3640 Microcomputer Interfacing Week #3 Assembly Language Design and Structure

2 ENG3640 Fall Topics  Stopping a Program.  Software Delay Routine.  Assembly Language Design and Structure.  Program Structure and Organization.  D-Bug12 Utility Routines.  The CPU12 Instruction Set  Data Transfer  Logical Operations  Using the Stack  Subroutine Calls  Arithmetic Operations (Add, Sub, Mult, Div)

3 ENG3640 Fall Resources  Huang, Chapter 4 Sections  2.6 Program Loops  2.10 Program Execution Time  4.10 Using D-Bug12 Functions

4 ENG3640 Fall Stopping a Program 1. STOP: stop processing stops internal clocks, puts the processor in the standby mode recovery from STOP may be accomplished by RESET^ or an interrupt 2. Stop_here BRA Stop_here BRA (rel) Branch always Opcode: 20 Operation: PC ← (PC) + $002 + rr 3. End Directive: any statement following the END directive will be ignored by the assembler. 4. SWI: software interrupt When executed it stacks the registers, and executes an ISR. Works like a break point in your program. RECOMMENDED!

5 ENG3640 Fall Software Delay Routines  Software delay routines are used to synchronize the execution of a program with respect to time: 1. Temporarily display a message 2. To debounce a switch on a keyboard! 3. To wait for an EEPROM to be erased.  So in many applications the execution of a routine must be timed to meet external requirements.

6 ENG3640 Fall Subroutine Program Flow Bsr func func rts The rts instruction returns program flow to the instruction following the last subroutine call! bsr saves the PC on the stack before going to func.

7 ENG3640 Fall Delay Routines: Issues  In order to design a software delay routine, we must know how to calculate the time it takes to execute the instructions that make up the routine!  Main problem with software delays is that their timing characteristics change if interrupts are used!  Also, the CPU has to have a deterministic instruction execution time (i.e. No pipelining!)

8 ENG3640 Fall Instruction Timing  The instruction execution time is determined by: 1. Bus Frequency of the CPU 2. Number of cycles required by the instruction  The number of cycles depend on many things: 1. Size of opcode. 2. The number of arguments. 3. Size of the data bus. 4. Complexity of execution.

9 ENG3640 Fall Program Execution Time The number of cycles executed by each Instruction are detailed in the CPU12 Manual

10 ENG3640 Fall CPU12: Instruction Execution Time  To convert the number of cycles to time, we must know the bus frequency of the CPU  CPU12 bus frequency is based on the E-clock.  For the MC68HC12A4 the E-clock (F E ) is one half of the oscillator or crystal frequency found on the XTAL and EXTAL inputs.  The crystal frequency of the MC68HC12A4 is 16MHz, so F E = 8MHz

11 ENG3640 Fall CPU12: Total Execution Time  The total execution time (T ex ) is then given by: T ex = N x T E where N = total number of clock cycles T E = the E-clock period, 1/F E

12 12 Simple Delay: Implementation ldx #1 ; [2] E cycles loop psha ; [2] E cycles pula ; [3] E cycles psha ; [2] E cycles pula ; [3] E cycles nop ; [1] E cycle dbne x,loop ; [3] E cycles Total cycles  15 clock cycles (excluding 8MHz (125 ns)  125 x 15 = uS ENG3640 Fall 2012

13 13 Example1: Simple Delay Example: Write an instruction sequence to create 100 ms time delay. Solution: 1. Previous loop takes us 2. We have to find out the number that should be loaded with the index register x? ms / us  53,333

14 ENG3640 Fall Example2: 100ms Delay Example: Write an instruction sequence to create 100 ms time delay. ldx #53333 ; [2] E cycles loop psha ; [2] E cycles pula ; [3] E cycles psha ; [2] E cycles pula ; [3] E cycles nop ; [1] E cycle dbne x,loop ; [3] E cycles

15 ENG3640 Fall Subroutine Dly1ms ;*********************************************************************************** ; Subroutine Dly 1ms – 1ms delay loop. ; MCU : 68HC12, E=8MHz, no clock stretching, 16-bit bus ; Registers : Preserve index register x. ; Stack Reqs: 2 bytes stack space Dly1ms pshx ; [2] ldx #TC1MS ; [2] d1mslp dex ; [1] bne d1mslp ; [3/1] pulx ; [3] rts ; [5] We need to find the value of TC1MS!!

16 ENG3640 Fall Dly1ms N = 14 + (4 * TC1MS) ; 14 cycles outside the loop ; 4 cycles inside the loop For a delay of 1ms we need N = T EX /T E = 1ms/125ns = 8,000 cycles ; Recall T E = 1/F E This requires a loop count TC1MS of: TC1MS = (N-14)/4  1,  1,996

17 ENG3640 Fall Program Contents and Organization The objective is to illustrate the program organization and give an example of a programmable delay and show you how I/O ports can be used within the CPU Program Header 2. Equates (port definitions e.t.c.) 3. Constants 4. Variables 5. Main Program 6. Subroutines

18 ENG3640 Fall Program Contents: Header 1. Program Header 1. Program Header (functional description of program, list program dependencies, revision date, name) ;**************************************************** ;* A simple demonstration program ;* It generates 60 1-second, active low, pulses on PH0 ;* MCU : 68HC12A4, E= 8MHz ;* Monitor: D-Bug12 ;* ;* Date: 20/09/2012 ;* Author: Shawki Areibi ;*****************************************************

19 ENG3640 Fall Program Contents: Equates 1. Equates: should follow the program header. By using equates you can use symbol names to make the code more readable. ;****************************************************************** DDRH EQU $25 ; Port Definition PORTH EQU $24 BIT0 EQU % TC1MS EQU 1996 ; Delay Count for 1ms ;******************************************************************

20 ENG3640 Fall Program Contents: Constansts & Variables 1. Stored constants : The stored constants are defined after all the program code. 2. Variables : Variables are places at the end of the program. One thing unique about variables is that they must be placed in RAM. During development the whole program is placed in RAM, so there is not another origin statement for the variables. ;********************************************************************************* ; Constants ;********************************************************************************* InitCnt fcb 60 ; initial pulse count ;********************************************************************************* ; Variables ;********************************************************************************* CurCnt rmb 1 ; LED flash counter

21 ENG3640 Fall Program Contents: Main Program 1. Main Program: After equates there should be an origin directive to define the starting location of the program code. The main program follows the ORG directive. ;****************************************************************** ORG $0800 Main bset DDRH, BIT0 ; Initialize PORTH, BIT0 bset PORTH, BIT0 movb InitCnt, CurCnt ; Initialize pulse counter ; InitCnt defined in Constant Section ; CurCnt defined in Variable Section ;****************************************************************** ;* Main loop for output pulse generation ;******************************************************************

22 ENG3640 Fall Cont … Main Program ORG $0800 Main ; Initialization Section ;****************************************************************** ;* Main loop for output pulse generation ;****************************************************************** Pulse bclr PORTH, BIT0 ; Turn pulse off ldd #250 ; Wait for 250ms jsr WaitDms ; WaitDms is a programmable delay bset PORTH, BIT0 ; Turn pulse on ldd #750 jsr WaitDms dec CurCnt ; Count pulses? bne pulse ; No: Another pulse swi ; Yes: Return to monitor

23 ENG3640 Fall Program Contents: Subroutines 1. All subroutines and interrupt service routines, should follow the main program. Subroutines themselves should never be contained within the main program code or another subroutine. ;*********************************************************************************** ; Subroutine WaitDms – A programmable delay in ms. ; Arguments : The number of ms is passed in ACCD ; Registers : Preserve all registers except CCR. ; Stack Reqs: 6 bytes stack space ; Req. subs : Dly1ms ;************************************************************************************ WaitDms pshd ; preserve ACCD msdlp jsr Dly1ms ; execute 1ms ACCD times subd #1 bne msdlp puld rts

24 ENG3640 Fall Program Contents: Subroutines ;*********************************************************************************** ; Subroutine Dly 1ms – 1ms delay loop. ; MCU : 68HC12, E=8MHz, no clock stretching, 16-bit bus ; Arguments : None ; Registers : Preserve all registers except CCR. ; Stack Reqs: 2 bytes stack space ; Req. subs : None ;************************************************************************************ Dly1ms pshx ; preserve IX ldx #TC1MS ; execute loop TC1MS times d1mslp dex bne d1mslp pulx rts

25 ENG3640 Fall Program Organization ;********************************************** ; Program Header ;********************************************** ; Equates ;********************************************** ; Constants ;********************************************** ; Variables ;********************************************** ; Main Program ;********************************************** ; Subroutines ;**********************************************

26 ENG3640 Fall D-Bug12 Utility Routines  A stable operating environment is required to develop microcontroller software.  One of the simplest most economical development environments consist of a monitor/debugger program that resides in ROM and executes in the target environment.  A ROM monitor provides 1. Environment for controlled execution of software 2. Utility routines to aid in testing new algorithms.

27 ENG3640 Fall D-Bug12 Utility Routines  The utility routines are presented as C function definitions in the Motorola Application Note ``Using and Extending D- Bug12 Routines” because the D-Bug12 was written almost entirely in C.  The utility routines are usable when: 1. Programming in C 2. Programming in Assembly Language!

28 ENG3640 Fall D-Bug12 Utility Routines (check Appendix C of Lab Manual of Web) Function DescriptionVector Table Address main()Start of D-Bug12$EE80 getchar()Get a character from SCI0 or SCI1$EE84 putcharSend a character out SCI0 or SCI1$EE86 getCmdLine()Obtain a line of input from the user$EE8A sscanhex()Convert an ASCII hex string to binary integer$EE8E isxdigit()Checks for membership in set[0..9,a..f,A..F]$EE92 toupper()Converts lower case characters to upper case$EE94 isalpha()Checks for membership in the set [a..z,A..Z]$EE96 out2hex()Displays 8-bit number as 2 ASCII hex characters$EE9C writeEEByte()Write a data byte to on-chip EEPROM$EEA6 eraseEE()Bulk erase on-chip EEPROM$EEAA

29 ENG3640 Fall Assembly Source for isdigit( c ) ;*********************************************************** ; isdigit(c) ; Description: A routine to check if an ASCII char is a digit (0..9) ; Arguments: Char is passed in ACCB ; Return value is passed in ACCB and Z bit of CCR ;*********************************************************** Isdigit cmpb #’0’ blo isd_not Isd_9 cmpb #’9’ bhi isd_not ldab #1 bra isd_rtn Isd_not clrb Isd_rtn rts

30 ENG3640 Fall Assembly Language Interface Calling a function from assembly language is simple. 1. First push the parameters onto the stack in the proper order. 2. Call the function with a JSR instruction. 3. The JSR instruction uses a form of indexed indirect addressing that treats the Program Counter as an index register. 4. Results are returned in the D Accumulator. 1. Char values returned in the D Accumulator are located in B 2. Boolean function results are zero for False and non-zero for True. 5. Called functions preserve only the content of the stack pointer. If other CPU12 register values must be preserved, they must be pushed onto the stack before any of the parameters and restored after deallocating the parameters.

31 ENG3640 Fall int getchar(void) Function DescriptionVector Table Address Getchar()Get a character from SCI0 or SCI1$EE84  The getchar() function retrieves a single character from the control terminal SCI  If a character is not available in the SCI Receive Data Register when the function is called, getchar() waits until one is received.  Because the character is returned as an int, the 8-bit character is placed in the B Acc.

32 ENG3640 Fall Int printf(char *format) Function DescriptionVector Table Address Printf()Print arguments to output device (monitor screen)$EE88  The printf() function is used to convert, format, and print its arguments as standard output (the output device could be the monitor screen, printer, LCD, etc) under the control of the format string pointed to by format.  Formatted characters supported by the printf() function are  d,i  signed decimal number  c  single character  s  string until a `\0’ (NULL)

33 33 Example: Utilizing getchar(), printf() CR EQU $0D ; ASCII for Carriage Return LF EQU $0A ; ASCII for Line Feed getchar EQU $EE84 ; Address of getchar() printf EQU $EE88 ; Address of printf() ORG $1000 ; Start address of vars/constants msg db “char pressed is %c”,CR,LF,0 ORG $1100 ; Start address of main program getnewval LDX getchar ; load address of getchar subroutine JSR 0,X ; get char from keyboard CMPB #$1B ; check if the char is an ESC char BEQ terminate ; jump to end of program PSHD ; push char on stack for printf subroutine LDD #msg ; second parameter in ACCD LDX printf ; load address of printf subroutine JSR 0,X ; print message on terminal BRA getnewval ; repeat getting new chars terminate SWI ; end of program ENG3640 Fall 2012

34 34 Instructions: Classificaions  Data handling (Data Transfer)  Arithmetic (Addition, Subtraction,..)  Subroutines  Logic Operations (AND, OR,..)  Bit Test and Manipulation  Branches and Jumps  Conditional Branches

35 ENG3640 Fall Data Handling: Register Loads CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] LDAA(M)  ACCA X X X X X X LDAB(M)  ACCB X X X X X X LDD(M:M+1)  ACCD X X X X X X LDS(M:M+1)  SP X X X X X X LDX(M:M+1)  IX X X X X X X LDY(M:M+1)  IY X X X X X X LEASEA  SP X LEAXEA  IX X LEAYEA  IY X To transfer an immediate value or a value from memory to a register, a load instruction is used.

36 ENG3640 Fall Load Effective Address  The last three instructions in previous table are “load effective address instructions”.  Load Effective Address Example leas 4, SP ; SP+4  SP leay d, y ; IY+ACCD  IY

37 ENG3640 Fall Data Handling: Register Store CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] STAAACCA  (M) X X X X X STABACCB  (M) X X X X X STDACCD  (M:M+1) X X X X X STSSP  (M:M+1) X X X X X STXIX  (M:M+1) X X X X X STYIY  (M:M+1) X X X X X To transfer data from a register to memory, a store instruction is used.

38 38 Transfers and Exchanges CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] TFR R1,R2R1  R2 X SEX R1,R2 Sign Extend R1  R2 R1 = A, B, CCR X TABACCA  ACCB X X TAPACCA  CCR X X TBAACCB  ACCA X X TPACCR  ACCA X X TSXSP  IX X X TSYSP  IY X X TXSIX  SP X X TYSIY  SP X X EXG R1,R2R1 <  R2 X XGDXACCD <  IX X X To move data between two registers, transfer and exchange instructions are used.

39 ENG3640 Fall Transfers and Exchanges  The CPU12 added a general-purpose transfer and a general- purpose exchange to replace the CPU11 register specific transfers and exchanges. tfr a, b ; ACCA  ACCB tab ; ACCA  ACCB (Compatible CPU11)  Note: the tab instruction affects the CCR, whereas the tfr has no effect on the CCR!  If a transfer occurs from a 16-bit register to an 8-bit register, the Least Significant Byte of the source register is copied to the destination register.  If a transfer occurs from an 8-bit register to a 16-bit register, CPU12 automatically performs a sign extension into the most significant byte of the destination register.

40 ENG3640 Fall Move Instructions CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] MOVB(M1)  (M2) X X X MOVW(M1:M+1)  (M2:M2+1) X X X  The memory-to-memory move instruction is another new instruction that significantly improves code efficiency in the CPU12.  It enables you to either move data from one memory location to another or move immediate data into a memory location without using CPU register.

41 ENG3640 Fall Move Instructions Examples ************************************************************** movb #$0F, PORTJ ; $0f  PORTJ ldaa #$0F ; CPU11 Equivalent staa PORTJ *************************************************************** movw 0,x,0,y ; (IX:IX+1)  (IY:IY+1) ldd 0,x ; CPU11 Equivalent std 0,y

42 ENG3640 Fall The 68HC12 has shift and rotate instructions that apply to a memory location, accumulators A, B and D. A memory operand must be specified using the extended or index addressing modes. Logical Shift Shift Left (Memory,A,B,D): LSL,LSLA,LSLB,LSLD Shift Right (Memory,A,B,D): LSR,LSRA,LSRB,LSRD Similar to a Logical shift, but the sign bit remains unchanged. Arithmetic Shift, Similar to a Logical shift, but the sign bit remains unchanged. Shift Left (Memory,A,B,D): ASL,ASLA,ASLB,ASLD Shift Right (Memory,A,B,D): ASR,ASRA,ASRB Cyclic Shift (or Rotation) Left (Memory,A,B): ROL, ROLA,ROLB Right (Memory,A,B): ROR, RORA,RORB Shift and Rotate Instructions

43 ENG3640 Fall Shift and Rotate Instructions A common application for the shift and rotate? multiplication and division. Shifts can be used to multiply or divide by constant powers of 2.

44 ENG3640 Fall Boolean Logic, Bit Manipulation CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] ANDAACCA.(M)  ACCA X X X X X X ANDBACCB.(M)  ACCB X X X X X X ANDCCCCR.(M)  CCR EORAACCA XOR (M)  ACCA X X X X X X EORBACCB XOR (M)  ACCB X X X X X X ORAAACCA + (M)  ACCA X X X X X X ORABACCA + (M)  ACCB X X X X X X ORCCCCR + (M)  CCR X COMA (B)ACCA’  ACCA X X COM(M)’  (M) X X X X Boolean logic functions are important for bit manipulation such as setting, clearing or inverting individual bits in a word.

45 ENG3640 Fall Bit Manipulation “Clearing Bits” 1. Clearing Bits: use the AND Instruction X.1 = X X.0 = 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A A 3 A 2 A 1 A 0

46 ENG3640 Fall Bit Manipulation “Setting Bits” 1. Setting Bits: use the OR Instruction X + 1 = 1 X + 0 = X A 7 A 6 A 5 A 4 A 3 A 2 A 1 A A 7 A 6 A 5 A

47 ENG3640 Fall Bit Manipulation “Inverting Bits” 1. Inverting Bits: use the XOR Instruction X (XOR) 1 = X’ X (XOR) 0 = X A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 XOR A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 ’

48 ENG3640 Fall CCR Flag Manipulation CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] CLC0  C X X CLI0  I X X CLV0  V X X SEC1  C X X SEI1  I X X SEV1  V X X There are individual instructions for setting and clearing CCR flags

49 49 Stack The Stack  Conceptually, a stack is a list of data items whose elements can be accessed from only one end.  A stack element has a top and a bottom.  The operation that adds a new item to the top is called push.  The top element can be removed by performing an operation called pop or pull.  The Stack Pointer (SP) points to the top element or to the memory location above the top element.

50 ENG3640 Fall Using the STACK MnemonicOperationEquivalent Operation PSHASP - 1  SP, ACCA  (SP)staa 1, -SP PSHBSP - 1  SP, ACCB  (SP)stab 1, -SP PSHCSP - 1  SP, CCR  (SP)none PSHDSP - 2  SP, ACCD  (SP:SP+1)std 2, -SP PSHXSP – 2  SP, IX  (SP:SP+1)stx 2, -SP PSHYSP – 2  SP, IY  (S):SP+1)sty 2, -SP PULA(SP)  ACCA, SP + 1  SPLdaa 1,SP+ PULB(SP)  ACCB, SP + 1  SPLdab 1,SP+ PULC(SP)  CCR, SP + 1  SPnone PULD(SP:SP + 1)  ACCD, SP + 2  SPLdd 2, SP+ PULX(SP:SP + 1)  IX, SP + 2  SPLdx 2, SP+ PULY(SP:SP + 1)  IY, SP + 2  SPLdy 2,SP+ The stack is LIFO data structure. It is an ideal data structure for temporarily storing data from nested routines

51 ENG3640 Fall Stack Instructions  The CPU12 stack is used by the user program and automatically by the CPU for subroutine calls and interrupts.  The stack is used to  Store the return address of subroutines.  Communicate variables to the calling subroutine  To return values from a subroutine.  To save the values of registers when an external/internal interrupt occurs

52 ENG3640 Fall Stack Usage Rules Initialize the stack pointer: Typically the stack pointer is initialized to the last byte of user RAM. This is because the stack grows into lower addresses. Balance the stack: Always make sure there are as many bytes pulled off the stack as there are bytes pushed onto the stack! Do Not Use Data Above the Stack Pointer: Data will be overwritten and destroyed! Do Not Use the Stack haphazardly for temporary storage: A common bug is caused by pushing data onto the stack, and then missing the pull because of a conditional branch (i.e., unbalanced stack).

53 ENG3640 Fall Subroutines  An assembly language program is made up of a main program and subroutines.  If the system is interrupt driven, there will be interrupt service routines (ISR).  Hierarchy:  Designing a program hierarchically creates a more reliable and reusable program.  In order to design hierarchically, you must use structured programming constructs and carefully designed routines.

54 ENG3640 Fall Subroutines  The CPU12 has several instructions to implement subroutines.  Traditional subroutine instructions used for 64K-byte systems are BSR, JSR, RTS CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] BSRSP – 2  SP X PC  (SP:SP+1) PC + rel  PC JSRSP – 2  SP X X X X X PC  (SP:SP+1) AD  PC RTS(SP:SP+1)  PC X X SP + 2  SP

55 55 Subroutines (CALL, RTC)  The CPU12 has new instructions to implement subroutines.  The new instructions are used for subroutines that may fall on different memory pages (Expanded Memory).  Writing assembly programs to be run in expanded memory requires an assembler that supports this feature!. CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] CALLSP – 2  SP X X X PC  (SP:SP+1) SP – 1  SP PPAGE  (SP) Page  PPAGE A D  PC RTC(SP)  PPAGE X SP + 1  SP (SP:SP+1)  PC SP + 2  SP ENG3640 Fall 2012

56 56 Subroutine Program Flow Bsr func func rts The rts instruction returns program flow to the instruction following the last subroutine call! jsr/bsr saves the PC on the stack before going to func.

57 ENG3640 Fall Passing Parameters  When passing parameters between two routines, we can pass the data, or reference to the data. 1.The simplest and most efficient method for passing parameters is to use a register. The calling routine simply places the parameter in a register before jumping to the subroutine. However we are limited by number of registers. 2.The most versatile method to pass parameters is to use the stack. As long as there is enough stack space, any number of parameters can be passed.

58 58 Issues in Subroutine Calls 1. Parameter passing -Use registers (few parameters) -Use the stack -Use global memory 2. Returning results -Use registers (few results) -Use the stack (caller creates a hole in which the result will be placed) -Use global memory 3. Local variable allocation -Allocated by the callee -The following instruction is the most efficient method of local variable allocation. leas -n,sp; allocate n bytes in the stack for local variables 4. Local variable deallocation -performed by the subroutine - The following instruction is the most efficient method of local variable deallocation. leasn,sp; deallocate n bytes from the stack

59 ENG3640 Fall Stack Usage Conventions

60 60 Stack Frame -The region in the stack that holds incoming parameters, the subroutine return address, local variables, and saved registers is referred to as stack frame. - The stack frame is also called activation record. ENG3640 Fall 2012

61 61 Example 4.10 Draw the stack frame for the following program segment after the leas –10,sp instruction is executed: ldd#$1234 pshd ldx#$4000 pshx jsrsub_xyz … sub_xyzpshd pshx pshy leas-10,sp … Solution: The stack frame is shown in Figure 4.10.

62 ENG3640 Fall Subroutine Implementation C Function Example For (j = 0; j<10; ) { j = FuncA(j); } C Assembly Code ldaa #0 ; initialize j Loop: cmpa #10 ; Compare j to 10 bge EndLoop ; Else (j < 10) psha ; Push Parameter J onto Stack des ; Allocate space for return value bsr FuncA ; Call FuncA pula ; Pull return value from Stack ins ; Deallocate space from Stack bra Loop ; Repeat loop EndLoop: FuncA: ldaa 3,sp ; load parameter from stack adda #2 ; Add 2 to A staa 2, sp ; Store return value to stack rts ; Return from FuncA Byte FuncA(byte a) { return a + 2; } ….. $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF $4000 SP: RetVal: Param: Initial SP:

63 ENG3640 Fall Subroutine Implementation Addr Opcodes Label Instruction Description 0000 main … bsr sub1 ;SP–2 -> SP, PC => (SP:SP+1), PC+rel->PC X012 …. X030 20ce bra main ; PC + rel = main -> PC X032 sub1 …. X jsr sub2 ;SP – 2 -> SP, PC ->(SP:SP+1), sub2 -> PC X043 …. X050 3d rts ;(SP:SP+1) -> PC, SP+2 -> SP X051 sub2 …. X060 3d rts ;(SP:SP+1) -> PC, SP+2 -> SP

64 ENG3640 Fall Basic Subroutine Techniques  Never branch out of or into a subroutine: this can cause a disastrous bug! A subroutine should always have a single entry point and a single exit.  Preserve Registers: we have two choices, either preserve the registers in the calling routine, or preserve the registers in the subroutine.  Subroutine Documentation: One of the advantages of using subroutines is for reuse and portability. If the routine is well documented it can be reused easily i.e. Subroutine name and function, MCU and monitor dependencies, Stack requirements …..

65 ENG3640 Fall Addition Instructions CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] ABAACCA+ACCB  ACCA X X ABXACCB+IX  IX X X ABYACCB+IY  IY X X ADCA(M)+ACCA+C  ACCA X X X X X X ADCB(M)+ACCB+C  ACCB X X X X X X ADDA(M)+ACCA  ACCA X X X X X X ADDB(M)+ACCB  ACCB X X X X X X ADDD(M:M+1)+ACCD  ACCD X X X X X X DAADecimal Adjust ACCA X X Addition instructions can be either 8-bit additions or 16-bit additions.

66 ENG3640 Fall Bit Binary Addition  Example ldaa #$3a ; $3a  ACCA adda #$7c ; ACCA + $7c  ACCA The CPU operation 1111 H N Z V C $3A $7C $B NOTE: The CPU does not know if the arguments are signed, unsigned or BCD!! Flags?

67 ENG3640 Fall Affected Flags?  The flags are set according to the Boolean formulas in the adda instruction description.  The half-carry flag, H, indicates a carry out of bit 3.  The negative flag, N, indicates a negative result, i.e. a result is negative if bit 7 of result is set.  The zero flag, Z, is not set since result is not zero!  The overflow flag, V, is set since the addition resulted in a two’s complement overflow (How can we easily tell?) If two arguments have the same sign and the result has the opposite sign, then the V flag is set.

68 ENG3640 Fall Unsigned Interpretation  If the arguments are both unsigned numbers, the addition can be interpreted as follows: $3A  58 $7C  $B6  182  8-bit unsigned numbers can range from 0 to 255. If the result exceeds 255, then the C flag will be set, and the 8-bit result will be incorrect!  So if you are using unsigned numbers and the C flag were set we would branch to an error routine or use C flag to calculate a 16-bit result.

69 ENG3640 Fall Signed Interpretation  If the arguments are both signed numbers, the addition can be interpreted as follows: $3A  +58 $7C  $B6  (-74)  8-bit signed numbers can range from -128 to If the result exceeds the range, the overflow flag, V, will be set.  So if you are using signed numbers and the V flag were set, we know that the result is incorrect.

70 ENG3640 Fall Subtraction Instructions CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] SBAACCA-ACCB  ACCA X X SBCAACCB-(M)-C  ACCA X X X X X X SBCBACCB-(M)-C  ACCB X X X X X X SUBAACCA-(M)  ACCA X X X X X X SUBBACCB-(M)  ACCB X X X X X X SUBDACCD-(M:M+1)  ACCD X X X X X X NEG0 - (M)  (M) X X X NEGA0 - ACCA  ACCA X X NEGB0 - ACCB  ACCB X X Subtraction instructions can be either 8-bit/16-bit subtractions or negate instructions

71 ENG3640 Fall Multiplication CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] EMUL16 x 16 Multiply, Unsigned X EMULS16 x 16 Multiply, Signed X MUL8 x 8 Multiply, Unsigned X X The CPU12 multiplication instructions represent a significant improvement over the CPU11. The CPU11 mul executes in 10 cycles whereas the CPU12 mul takes only 3 cycles.

72 ENG3640 Fall Multiplication: MUL unsigned 8-bit unsigned AB X 16-bit unsigned D The mul instruction can be used for integers or mixed numbers.

73 ENG3640 Fall Unsigned Multiply Instructions Example: Mult ldaa #$20 ;$20  ACCA ldab #$35 ;$35  ACCB mul ; $20 x $35 = 06A0  ACCD Interpretation (8-bit integers) $20  32 x $35  x $06A0  1696

74 ENG3640 Fall Division CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] EDIV32 by 16 Divide, Unsigned X EDIVS32 by 16 Divide, Signed X FDIV16 by 16 Fractional Divide, unsigned X X IDIV16 by 16 integer Divide, unsigned X X IDIVS16 by 16 integer, Divide, signed. X CPU11 The CPU12 division instructions represent a significant improvement over the CPU11. The CPU11 idiv and fdiv execute in 41 cycles whereas the CPU12 version take only 12 cycles.

75 ENG3640 Fall Unsigned Integer Division: IDIV 16-bit unsigned DX / X dividenddivisor quotient 16-bit unsigned remainder D Condition codes Z: set if result is $0000; cleared otherwise V: 0, cleared C: set if denominator was $0000; cleared otherwise

76 ENG3640 Fall Compares and Tests CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] CBAACCA-ACCB X X CMPAACCA-(M) X X X X X X CPDACCD-(M:M+1) X X X X X X CPSSP – (M:M+1) X X X X X CPXIX – (M:M+1) X X X X X X CPYIY – (M:M+1) X X X X X X TST(M) - 0 X X X X TSTAACCA - 0 X X TSTBACCB - 0 X X Compare instructions are used to compare two arguments and set the appropriate flags for a conditional branch instruction.

77 ENG3640 Fall Cont.. Compare and Test Remarks: 1. Operations performed are similar to subtraction instructions except that the result is not saved! 2. The CBA instruction compares content of ACC A and ACC B and sets Z if result is $00, sets N if MSB of result is `1’, sets V if two’s complement overflow resulted, and sets C if there was a borrow. 3. The test instructions are simply compare to zero. They are useful only for signed branches.

78 ENG3640 Fall Bit Test and Manipulation CPU12 Addressing Modes MnemonicOperationCPU11 INH IMM DIR EXT IDX[IDX] BITAACCA. (M) X X BITBACCB. (M) X X BCLR(M). Msk’  (M) X X X X BSET(M) | msk  (M) X X X X  bclr and bset are used to set or clear bits in a word in memory.  bita and bitb are bit testing instructions.

79 ENG3640 Fall Example: Bit Manipulation ************************************************************ * Clear MSB, LSB of memory location pointed to by Index register x ($81 = % ) bclr 0,x,$81 ************************************************************ * Set MSB of memory location pointed to by Index register y ($80 = % ) bset 0,y,$80

80 ENG3640 Fall Branch Instructions Four types of branch instructions: -Unary (unconditional) branch: always execute (e.g BRA) -Simple branches: branch is taken when a specific bit of CCR is in a specific status -Unsigned branches: branches are taken when a comparison or test of unsigned numbers results in a specific combination of CCR bits -Signed branches: branches are taken when a comparison or test of signed quantities results in a specific combination of CCR bits Two categories of Branches -Short Branches: in the range of -128 ~ +127 bytes (8-bit offset is added) -Long Branches: in the range of 64KB (16-bit offset is added)

81 ENG3640 Fall Jump Instruction Label Instruction ********************************************************* START CBA BEQSKIP JMPNOT_EQUAL SKIP INCA NOT_EQUAL END The program counter will be loaded by the address NOT_EQUAL

82 ENG3640 Fall Conditional Branches 1.The branch and jump instructions always perform the jump or branch when they are executed (unconditional!) 2.Conditional branch instructions branch only if certain conditions are satisfied. 3.The conditions are always based on the contents of the condition code register. 4.Conditional branches are used to implement conditional and loop constructs. 5.The CPU11 and CPU12 have different conditional branches (simple, conditional branches for signed numbers and unsigned numbers)

83 ENG3640 Fall  When a short-branch instruction is executed, a signed 8- bit offset is added to the value in the program counter when a specified condition is met.  The numeric range of the short branch offset value is $80 (- 128) to $7F (+127) from the address of the instruction immediately following the branch instruction. Short Branch Instructions

84 84 Assembly Programming – Programming Concepts if(a>=20) { // if body } If-Then C Code: If-Then Assembly Code: cmpa, #20 ; If Cond. (A>=20) blo EndIf ; Branch !(A>=20)=>(A<20) ; If Body EndIf: If Cond. !(A>=20) If Body A>=20 ENG3640 Fall 2012

85 85 Assembly Programming – Programming Concepts if(a>=20) { // if body } else { // else body } If-Then-Else C Code: If-Then-Else Assembly Code: cmpa, #20 ; If-Else Cond. (A>=20) blo Else ; Branch !(A>=20)=>(A<20) ; If Body bra EndIf ; Branch EndIf Else: ; Else Body ; EndIf: If–Else Cond. A>=20 Else Body !(A>=20) If Body ENG3640 Fall 2012

86 86 Assembly Programming – Programming Concepts for(J=0; J<10; J++) { // loop body } For Loop C Code: J=0 Loop Cond. !(J<10) Loop Body J++ J<10 For Loop Assembly Code: ldaa #0 ; Loop Init. (J=0) Loop: cmpa #10 ; Loop Cond. (J<10) bge EndLoop ; Branch !(J (J>=10) ; Loop Body adda #1 ; Loop Iter. (J++) bra Loop ; Repeat Loop EndLoop: ENG3640 Fall 2012

87 87 Assembly Programming – Programming Concepts while(i!=0) { // loop body } While Loop C Code: Loop Cond. !(i!=0) Loop Body i!=0 While Loop Assembly Code: Loop: cmpa, #0 ; Loop Cond. (i!=0) beq EndLoop ; Branch !(i!=0)=>(i==0) ; Loop Body bra Loop ; Repeat Loop EndLoop: ENG3640 Fall 2012

88 88  For every short branch instruction, a corresponding long branch instruction exists.  When a long- branch instruction is executed, a signed 16-bit offset is added to the value of the program counter when a specific condition is met. Long Branch Instructions

89 ENG3640 Fall Simple Conditional Branches Branch Complementary Branch Test Mnemonic Condition TESTMnemonicCondition R = MBEQZ = 1R =/ MBNEZ = 0 CarryBCSC = 1No CarryBCCC = 0 PositiveBPLN = 0NegativeBMIN = 1 OverflowBVSV = 1No OverflowBVCV = 0 AlwaysBRA ---NeverBRN ---  Are all based on the value of a single CCR flag.  Branch never, brn on the CPU11 can be used as a three cycle no- op instruction. However on the CPU12 it takes only a single cycle so it has no advantage over the nop instruction.

90 ENG3640 Fall Bit Conditional Branches CPU12 Addressing Modes MnemonicConditionCPU11 INH IMM DIR EXT IDX[IDX] BRCLR(M).msk = 0 X X X X BRSET(M)’.msk = 0 X X X X  BRCLR and BRSET are branch instructions that are conditional on individual bits or a bit field within a word.  Syntax is brclr M, msk, A D brset M, msk, A D Where: M = memory location containing bits to be tested, msk = the bit mask, A D = destination address

91 ENG3640 Fall Example ************************************************************ * Branch to bar if bits 7 and 3 of out_reg are clear brclr out_reg,% ,bar Note: The operation of these two instructions is the same as the code using logic instructions. ************************************************************ * Branch to bar if bits 7 and 3 of out_reg are set ldx #out_reg brset 0,x,% ,bar

92 Cont … CONDITIONAL BRANCH INSTRUCTIONS DECREMENT & BRANCH DBEQ COUNTER - $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC DBNE COUNTER - $01, COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC INCREMENT & BRANCH IBEQ COUNTER + $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC IBNE COUNTER + $01 COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC TBEQ IF COUNTER = 0, THEN PC+$ REL PC TBNE IF COUNTER <>0, THEN PC+$ REL PC FUNCTIONMNEMONIC OPERATION TEST & BRANCH 92ENG3640 Fall 2012

93 93 Example: ************************ ldx #20 loop: nop psha pula dbne x,loop ************************ ldx #FA loop: nop psha pula ibne x,loop

94 ENG3640 Fall

95 ENG3640 Fall Flow Diagrams  Flow diagrams are a widely used tool for graphically designing and documenting programs.  They provide a good way to visualize the program structure.  They are simple and widely used.  The main problem with flow diagrams is that they can be time consuming to create.

96 ENG3640 Fall Process Blocks  A process block represents a structured block of code. To be structured, it always has a single entrance and a single exit

97 ENG3640 Fall Decision Blocks  Decision blocks are used to conditionally execute processes.  They represent a high-level language if and an assembly language conditional branch instruction.

98 ENG3640 Fall Connectors  There are two types of connectors used: 1. Start and termination connectors (represent entrance and exit of a flow diagram). 2. Continuation connectors (used if a flow diagram is complex and spans more than a single page).

99 ENG3640 Fall Sequence Construct  The first and most obvious construct is a simple sequence of processes.

100 ENG3640 Fall If Construct  The if construct is used to conditionally execute a process. The if construct translates to a decision block in the flow diagram and a conditional branch in assembly code.

101 ENG3640 Fall If-Else Construct  The if-else construct is used to conditionally execute one of two mutually exclusive processes.

102 ENG3640 Fall If-Else-If-Else Construct  The if-else-if-else construct is used to conditionally execute one of several mutually exclusive processes.

103 ENG3640 Fall The Case Construct  The case construct is essentially the same as the if- else-if-else construct.

104 ENG3640 Fall The Do-While Loop  The do-while loop runs a process, and if a condition is true, it repeats the process.

105 ENG3640 Fall The While Loop  The while loop tests a condition, and if the condition is true, it repeats one or more processes.

106 ENG3640 Fall The For Loop  The for loop is a while loop with loop parameters and operations defined in an argument list.

107 ENG3640 Fall I/O Data Conversions

108 ENG3640 Fall I/O Data Conversions

109 ENG3640 Fall CPU11 versus CPU12  The CPU12 executes programs much faster than the CPU11 for several reasons: 1. CPU12 has a 16-bit data bus, so it can fetch opcodes and arguments with fewer bus cycles. 2. CPU12 can run at a higher bus frequency than the CPU It has added circuitry for complex instructions such as multiplies and divides. 4. The CPU12 also has an instruction queue that allows it to fetch the next instruction while it is executing the current instruction!

110 ENG3640 Fall I/O Data Conversions

111 ENG3640 Fall I/O Data Conversions

112 ENG3640 Fall I/O Data Conversions

113 ENG3640 Fall I/O Data Conversions

114 ENG3640 Fall Example The WriteEEByte() function is called as follows: WriteEEByte: EQU $FE1C ; ; ldab #$55 ; write $55 to EEPROM pshd ; place the data on the stack ldd EEAddress ; EEaddress to write data jsr [WriteEEByte, pcr] ; call the routine pulx ; remove the parameter from stack ;******************************************************************************** Could also use ldx WriteEEByte ; load the address of WriteEEByte() jsr 0,x ; call the routine


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