Download presentation

Presentation is loading. Please wait.

Published byToby Ford Modified about 1 year ago

1
EE800, U of S1 Decimal Floating-Point Arithmetic Dongdong Chen

2
EE800, U of S2 Objectives IEEE standard for Decimal Floating-Point (DFP) arithmetic (Lecture 1) –DFP numbers formats –DFP number encoding –DFP arithmetic operations –DFP rounding modes –DFP exception handling

3
EE800, U of S3 Objectives (Con.) Algorithm, architecture and VLSI circuit design for DFP arithmetic (Lecture 2) –DFP adder/substracter –DFP multiplier –DFP divider –DFP transcendental function computation

4
EE800, U of S4 Background The decimal computer arithmetic went out of style 25 to 30 years ago; no one uses it now." Is that true?

5
EE800, U of S5 Introduction Decimal is still essential for specific applications –Numbers in commercial databases are decimal –Extensive use decimal in commercial applications –Survey of commercial databases report –Decimal fixed-point or floating-point number How to process decimal computation –Software computation –Convert back to decimal representation –Problems

6
EE800, U of S6 Introduction (Con.) Errors from decimal and binary conversion –Example 1: represent 0.1 in DFP or BFP Decimal representation (BCD code): Binary representation: … 0.09… –Example 2: telephone billing Cost: 0.70; Tax: 5% BFP arithmetic: …8*(1.05)= … DFP arithmetic: 0.70*(1.05)=0.74 Decimal integer, fixed-point or floating-point? Decimal hardware or software solutions?

7
EE800, U of S7 DFP arithmetic defined in IEEE IBM computing systems include DFP hardware –IBM Power6, z9, z10 Intel include DFP software solution in system –Intel DFP software computation library DFP arithmetic IP blocks: –Basic DFP arithmetic IPs: DFP adder/substrcter, multiplier, divider, square root etc. –Transcendental DFP arithmetic IPs: DFP CORDIC, Logarithm, antilogarithm, reciprocal etc. Current Researches

8
EE800, U of S8 DFP Arithmetic in IEEE Review BFP arithmetic in IEEE How to define new DFP in IEEE

9
EE800, U of S9 BFP Floating-point representation Representation: –sign, exponent, significand (or mantissa): (–1) sign × significand × 2 exponent –more bits for significand gives more accuracy –more bits for exponent increases range IEEE 754 floating point standard: –single precision: 8 bit exponent, 23 bit significand –double precision: 11 bit exponent, 52 bit significand

10
EE800, U of S10 BFP floating-point Number Leading “1” bit of significand is implicit –Example: if the significand is …0, the actual significand is …0 This is called a normalized number; there is exactly one non-zero digit to the left of the point. –Unique representation of a number –We get a little more precision: there are 24 bits in the significand, but only 23 of them are stored.

11
EE800, U of S11 Exponent Exponent is “biased” to make sorting easier –all 0s is smallest exponent, all 1s is largest –The actual exponent is e-127 for single precision, and e-1023 for double precision –Bias of 127 for single precision and 1023 for double precision –By biasing the exponent and storing it before the significand, we can compare magnitudes as if they were unsigned integers. If e = ( ), the actual exponent is =4 If e = (93 10 ), the actual exponent is =-34

12
EE800, U of S12 BFP Floating-Point Formats

13
EE800, U of S13 BFP Floating-Point Formats (Con.) Negative Overflow Positive Overflow Expressible negative numbers Expressible positive numbers Positive underflow Negative underflow (2 – )× (2 – )× Biased exponent Fraction Positive and negative zero Biased exponent Fraction Positive and negative infinity exponent = 128 and fraction ≠ 0, It is called “not a number” or NaN 0 ∞

14
EE800, U of S14 Example Summary: FP representation (–1) sign × significand)×2 exponent – bias Example: –decimal: -.75 = -3/4 = -3/2 2 –binary: -.11 = -1.1 x 2 -1 –floating point: exponent = 126 = –IEEE single precision:

15
EE800, U of S15 Representation: –sign, exponent, significand (or mantissa): (–1) sign × significand × 10 exponent –more digits for significand gives more accuracy –more bits for exponent increases range representation: DFP formats: –decimal32: DFP storage format encoded in 32-bit –decimal64: DFP computational format encoded in 64-bit –decimal128: DFP computational format encoded in 128-bit DFP Number Representation

16
EE800, U of S16 DFP Number format 1-bit Sign (S) is defined as same as BFP format w+5-bit combination (G) to two subfield: –5-bit (G 0 …G 4 ) to encode: 2 MSBs of exponent; 1 MSD of significand; Not-a-Number (NaN); Inf; –W-bit(G 5 …G w+4 ) as a suffix 2 MSBs derived from G 0 …G 4, which consists of w+2-bit nonnegative biased exponent.

17
EE800, U of S17 DFP Exponent Exponent is “biased” to make sorting easier –Binary format (not decimal) –The actual exponent is e-101 for decimal32, e-398 for decimal64, e-6167 for decimal128 –Range of exponent is (emin−q+1) ≤ e ≤ (emax−q+1);

18
EE800, U of S18 DFP Number format (Con.) J×10-bit Trailing Significand (T) Field: –Densely packed decimal (DPD) encoding 3-digit decimal number encoded to 10-bit binary number DPD converted to binary coded decimal (BCD) –Binary integer decimal (BID) encoding decimal number encoded by binary integer –Non-normalized decimal significand (-1) 0 × × 10 2 (-1) 0 × × 10 1 –DFP number’s Cohort

19
EE800, U of S19 Parameters in DFP Format

20
EE800, U of S20 Example Summary: DFP representation (–1) sign ×(significand)×10 exponent-bias Convert -8.35×10 -2 to decimal64 –Sign bit: “1” negative, “0” positive (sign 1) –Exponent: =396 (8-bit “ ”) –Significand: 835 (50-bit DPD coding “0… D”) –Encoding of 5-bit MSBs ( G 0 …G 4 ) of Combinational field “01000” –Decimal-64 : “ …..00… ” “A D” (binary/hex)

21
EE800, U of S21 Not-a-Number: G 0 …G 4 “11111”; Infinite Number: G 0 …G 4 “11110”, sign of Inf according to the sign bit; Overflow: If DFP numbers with absolute values are larger than the largest DFP number (|v max |=(10 q - 1)×10 emax-q+1 ) then overflow occurs. Underflow: If DFP number are less than the smallest DFP number (|v min |=10 emin-q+1 ) then underflow occurs. If the absolute value of DFP number is less than 10 emin and larger than 10 emax-q+1, it produces subnormal. Normal number: The remaining exponent values and significands represent normal numbers. DFP special values

22
EE800, U of S22 Basic DFP arithmetic operations Two decimal-specific DFP operations –SameQuantum(DFP 1,DFP 2 ) –Quantize(DFP 1,DFP 2 ) DFP comparison operations –do not distinguish between redundant of the same number DFP conversion operations –DFP to BFP conversion (correctly rounded); –DFP to integer conversion Recommended DFP operations DFP Arithmetic Operations

23
EE800, U of S23 Basic DFP arithmetic operations Two decimal-specific DFP operations –SameQuantum(DFP 1,DFP 2 ) –Quantize(DFP 1,DFP 2 ) DFP comparison operations –do not distinguish between redundant of the same number DFP conversion operations –DFP to BFP conversion (correctly rounded); –DFP to integer conversion Recommended DFP operations DFP Arithmetic Operations

24
EE800, U of S24 Non-normalized decimal significand DFP number’s Cohort Standard defines the preferred (required) exponent (quantum) –Exact operation results: the cohort member is selected based on the preferred exponent (quantum) for a DFP result of that operation –Inexact operation results: the cohort member of least possible exponent is used to get the maximum number of significant digits DFP Number’s Cohort

25
EE800, U of S25 Five types of active rounding modes –roundTiesToEven –roundTiesToAway –roundTiesToPositive –roundTiesToNegative –roundTowardZero Correct rounding and Faithful rounding IEEE require to satisfy the correct rounded results for all DFP arithmetic operations DFP operations should satisfy all rounding modes DFP Rounding Modes

26
EE800, U of S26 Invalid operation: Operand is NaN; 0×Inf; quare- root of negative operand; default result is NaN Division by zero: if the dividend is a finite non-zero number and the divisor is zero. The default result is a +inf or −inf. Overflow operation: if the magnitude of a result exceeds the largest finite number representable in the format of the operation. Underflow operation: if the magnitude of a result is below 10 emin. Inexact: the correctly rounded result of an operation differs from the infinite precision result. DFP Exception Handling

27
EE800, U of S27 DFP Addition/Subtraction

28
EE800, U of S28 DFP Add/Sub Data flow

29
EE800, U of S29 Step 1: equalize the exponents –add the mantissas only when exponents are the same. –the number with smaller exponent should be shifting its point to the left, and the number with larger exponent should be shifting its point to right. –Rewriting the operand with the smaller exponent could result in a loss of the least significant digits –keep guard digit, round digit, and stick digit for the operand with smaller exponent DFP Addition

30
EE800, U of S30 DFP addition Step 2: add the mantissas x x x (234)x (234) x10 0 Step 3: Normalize the result if necessary

31
EE800, U of S31 DFP addition Step 4: Round the number if needed x10 0 = x10 0 Step 5: Repeat step 3 if the result is no longer normalized The final result is The correct answer is

32
EE800, U of S32 Guard bits To help minimize rounding problems, IEEE specifies that intermediate steps of operations must store guard digits - additional internal digits that increase the precision of the operations. Previous example: add one extra digit. IEEE requires one guard digit, one rounded digit and one sticky digit to make rounding more accurate.

33
EE800, U of S33 DFP add/sub

34
EE800, U of S34 General Description: Addition

35
EE800, U of S35 Example: Addition

36
EE800, U of S36 Example: Addition (Con.)

37
EE800, U of S37 DFU: IBM POWER6 and Z10

38
EE800, U of S38 High performance Implementation

39
EE800, U of S39 High performance Implementation

40
EE800, U of S40 High performance Implementation [12] A. Vázquez and E. Antelo“A High-performance Significand BCD Adder with IEEE Decimal Rounding” ARITH19, Portland. June

41
EE800, U of S41 Evaluation Results and Comparison [Proposed]: A. Vázquez and E. Antelo“A High-performance Significand BCD Adder with IEEE Decimal Rounding” ARITH19, Portland. June

42
EE800, U of S42 DFP Multiplication

43
EE800, U of S43 Scheme of decimal multiplier x : × y : = xy0: 5x xy1: 5x −x xy2 : x xy3: 10x −2x

44
EE800, U of S44 Partial product generation Generate XY i Y i {1,2,3…7,8,9} XY i is carry save format

45
EE800, U of S45 Partial product generation Solid Circles: BCD Sum (digit) Hollow Circles: Carry (bit) n-digit radix-10 CSA m-digit radix-10 counter

46
EE800, U of S46 Carry Save Adder Tree CSA Tree to Generate Multiplication Result

47
47 Flowchart of DFP Multiplier

48
48 Architecture of DFP Multiplier

49
49 Exception Detection & Handling Invalid operation –sNaN (pass significand of sNaN) –0 x ∞ (produce qNaN with significand 0) Overflow (and Inexact) –IE IP – SLA > Emax –Increase SLA until all LZs removed Underflow (and possibly Inexact) –IE IP – SLA < Emin –Decrease SLA until 0, then shift right Inexact

50
50 Implementation Highlights Leverage operands' LZCs –SC, SLA, and IE SIP Handle NaNs with minimal overhead –No dataflow modification –Coerce multiplicand or multiplier to 1 Support gradual underflow –No dataflow modification –Simply extend number of iterations Simple, control-based rounding scheme

51
51 Synthesis Results 64-bit (16 digit) operands, DPD encoded LSI Logic's gflxp 0.11um CMOS, 55ps FO4 Synopsys Design Compiler Results –Fixed-point119,653 um FO4s –Floating-point237,607 um FO4s Critical path –Fixed-point4:2 compressor (accumulator) –Floating-point128-bit barrel shifer

52
52 Applicability to Parallel Designs IE and IP shift generation Rounding scheme NaN handling Exception detection and handling On-the-fly sticky bit generation... NO

53
53 Sequential vs. Parallel Sequential –Less area –Potentially better cycle time Parallel –Less latency –Higher throughput

54
EE800, U of S54 DFP Division

55
EE800, U of S55 DFP Division Data Flow Unpacking Decimal Floating- Point Number Check for zeros and infinity Subtract exponents Divide Mantissa Normalize and detect overflow and underflow Perform rounding Replace sign Packing

56
EE800, U of S56 Unpacking and Sign Logic Step1: Unpacking Floating-Point Number Check for zeros and infinity (if F=0, Stop) Step2: Sign Process

57
EE800, U of S57 Exponent Subtraction Step3: Exponent Subtract

58
EE800, U of S58 Mantissa Division Step4: Mantissa Division Algorithms Choose here? 1. Restoring division 2. Non-restoring division 3. High-Radix division 4. Convergence division

59
EE800, U of S59 Normalization Step5 : Left shift over one bit is needed to make Mantissa result Normalized, also need to detect overflow and underflow For example: “ 0934 … ” Left shift one bit “ 934 … Should tell exponent and Ea=Eb-1

60
EE800, U of S60 Rounding and Packing Step6 : Truncate, Round-up, Round-to-nearest. Sometimes, the Rounding Policy above is not fair, according to IEEE Rounding standard: “ Round to nearest even ” is more better. Step7: Packing the Sign bit and Exponent bits and Significand bits together, detect the NaN, Infinity,

61
EE800, U of S61 High performance Implementation [1] L.-K. Wang and M. J. Schulte, “Decimal Floating-Point Division Using Newton-Raphson Iteration,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp , Sep

62
EE800, U of S62 High performance Implementation [2] Tomás Lang and Alberto Nannarelli, “A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture,”IEEE Transactions on Computers, pp727–739, IEEE, June 2007.

63
EE800, U of S63 High performance Implementation

64
EE800, U of S64 Evaluation Results and Comparison 1 : Synthesized with a STM 90-nm standard cell library DFP Divider [1] DFP Divider [2] Precision (digit)16 (decimal64) Cycle time (ns)0.571 # of cycles15020 Latency (ns)85.520

65
EE800, U of S65 DFP Transcendental Arithmetic

66
EE800, U of S66 Contents Introduction Decimal Logarithmic Converter Decimal Antilogarithmic Converter Conclusions Future Work

67
EE800, U of S67 32-bit DFP Logarithm coefficient is a non-normalized decimal Integer. To guarantee a 32-bit DFP Calculation, there need to keep 14-digit FXP logarithmic calculation. Example:

68
EE800, U of S68 32-bit DFP Antilogarithm Here: For 32-bit DFP: Example : To guarantee a 32-bit DFP calculation, there need to keep 8-digit FXP antilog calculation.

69
EE800, U of S69 Digit-Recurrence Algorithm (Log) The corresponding recurrences: Here: selected so that converges to 1 e j ∈｛ …0 1…7 8 9 ｝

70
EE800, U of S70 Digit-Recurrence Algorithm (Antilog) Any 7-digit fixed-point decimal input N: The corresponding recurrences: Here: selected so thatconverges to 0 e j ∈｛ …0 1…7 8 9 ｝

71
EE800, U of S71 Selection By Rounding (cont.) A scaled remainder is defined as: is achieved by Rounding W [j] e 1 is achieved by using look-up table, e 2 …e j can be obtained with selection by rounding Log: Antilog:

72
EE800, U of S72 Architecture: Decimal Log Converter

73
EE800, U of S73 Implementation Results Logic UtilizationUsedAvailable*Utilization # of Occupied Slices % Maximum Frequency 47.7 MHz # of Clock Cycles17 clock cycle *: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7 Critical Path Detail (ns): Reg2Mux2Mult 2ShifterMux5CLARoundTotal

74
EE800, U of S74 Architecture: Dec. Antilog Converter

75
EE800, U of S75 Implementation Results Logic UtilizationUsedAvailable*Utilization # of Occupied Slices % Maximum Frequency 51.5 MHz # of Clock Cycles11 clock cycle *: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7 Critical Path Detail (ns): Reg6MultMux4ShifterCLARoundTotal

76
EE800, U of S76 Comparison (with Binary FXP Log and Exponential Converters) similar dynamic range for the normalized coefficients. Binary reference available having the same digit- recurrence algorithm with Selection by Rounding. The radix-10 is close to radix-8.

77
EE800, U of S77 Comparison (cont.) (with Binary FXP Log and Exponential Converters) 1 : Synthesized with a TMSC 0.18-um standard cell library 2 : the area of 1-bit full adder 3 : the delay of 1-bit full adder Radix-10 Decimal 1 Radix-8 Binary [1] Log.Exp.Log.Exp. Precision (digit) Area (fa 2 ) Cycle time (T 3 ) # of cycles Latency (T 3 )

78
EE800, U of S78 Conclusions Achieved 32-bit DFP accuracy of decimal log and antilog results. Implemented them on FPGA and ASIC. Compare them with binary converters.

79
EE800, U of S79 EE990 April /18 Decimal Log and Antilog Converters Future Work The 64-bit and 128-bit DFP logarithm and antilog converters. The presented architecture can be optimized to achieve a faster speed or occupy a smaller area.

80
EE800, U of S80 Summary IEEE defines a DFP standard that defines –number representation in several precisions –correct DFP arithmetic operations –rounding modes Implementation of DFP Adder, Multiplier, Divider, Logarithmic and Antilogarithmic Converter Implementing and programming DFP are both really hard.

Similar presentations

© 2016 SlidePlayer.com Inc.

All rights reserved.

Ads by Google