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ECE 663 MOSFETs

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ECE 663 A little bit of history..

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Substrate Channel Drain Insulator Gate Operation of a transistor V SG > 0 n type operation Positive gate bias attracts electrons into channel Channel now becomes more conductive More electrons Source V SD V SG

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Substrate Channel Drain Insulator Gate Operation of a transistor Transistor turns on at high gate voltage Transistor current saturates at high drain bias Source V SD V SG

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Substrate Channel Drain Insulator Gate Source V SD V SG Start with a MOS capacitor

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ECE 663 MIS Diode (MOS capacitor) – Ideal

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W Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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ECE 663 ECEC EFEF EVEV EiEi Ideal MIS Diode n-type, V appl =0 Assume Flat-band at equilibrium qSqS

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ECE 663 Ideal MIS Diode n-type, V appl =0

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ECE 663 Ideal MIS Diode p-type, V appl =0

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ECE 663 Ideal MIS Diode p-type, V appl =0

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ECE 663 Accumulation Pulling in majority carriers at surface

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ECE 663 But this increases the barrier for current flow !! n + p n +

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ECE 663 Depletion

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ECE 663 Need CB to dip below E F. Once below by B, minority carrier density trumps the intrinsic density. Once below by 2 B, it trumps the major carrier density (doping) ! Inversion BB

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ECE 663 Sometimes maths can help…

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ECE 663 P-type semiconductor V appl 0 Convention for p-type: positive if bands bend down

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ECE 663 Ideal MIS diode – p-type CB moves towards E F if > 0 n increases VB moves away from E F if > 0 p decreases

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ECE 663 Ideal MIS diode – p-type At the semiconductor surface, = s

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s < 0 - accumulation of holes s =0 - flat band B > s >0 – depletion of holes s = B - intrinsic concentration n s =p s =n i s > B – Inversion (more electrons than holes) ECE 663 Surface carrier concentration ECEC EFEF

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ECE 663 Want to find , E-field, Capacitance Solve Poisson’s equation to get E field, potential based on charge density distribution(one dimension) EEE

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ECE 663 Away from the surface, = 0 and

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ECE 663 Solve Poisson’s equation: E = -d /dx d 2 /dx 2 = -d E /dx = (d E /d ).(-d /dx) = E d E /d E d E /d

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ECE 663 Do the integral: LHS: RHS: Get expression for E field (d /dx): Solve Poisson’s equation:

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ECE 663 Define: Debye Length Then: + for > 0 and – for < 0 > 0 E > 0 < 0 E < 0

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ECE 663 Use Gauss’ Law to find surface charge per unit area

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ECE 663 Accumulation to depletion to strong Inversion For negative , first term in F dominates – exponential For small positive , second term in F dominates - As gets larger, second exponential gets big B = (kT/q)ln(N A /n i ) = (1/ )ln(p p0 /√p p0 n p0 ) (n p0 /p p0 ) = e -2 B S > 2 B

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Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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ECE 663 Charges, fields, and potentials Charge on metal = induced surface charge in semiconductor No charge/current in insulator (ideal) metalinsulsemiconductor depletion inversion

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ECE 663 Electric Field Electrostatic Potential Charges, fields, and potentials

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ECE 663 Electric Field Electrostatic Potential Depletion Region

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ECE 663 Electric Field Electrostatic Potential = s (1-x/W) 2 W max = 2 s (2 B )/qN A B = (kT/q)ln(N A /n i ) Depletion Region

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Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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Couldn’t we just solve this exactly?

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U = U S = S U B = B Exact Solution d /dx = -( 2kT/qL D )F( B,n p0 /p p0 ) dU/F(U) = x/L D U USUS F(U) = [e U B (e -U -1+U)-e -U B (e U -1-U)] 1/2

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Exact Solution dU’/F(U’,U B ) = x/L D U USUS F(U,U B ) = [e U B (e -U -1+U) + e -U B (e U -1-U)] 1/2 = qn i [e U B (e -U -1) – e -U B (e U -1)]

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Exact Solution N A = 1.67 x Q inv ~ 1/(x+x 0 ) x 0 ~ L D. factor

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Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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ECE 663 Threshold Voltage for Strong Inversion Total voltage across MOS structure= voltage across dielectric plus s

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ox V i /t ox = s s /(W/2) Before Inversion After inversion there is a discontinuity in D due to surface Q inv V ox (at threshold) = s (2 B )/(W max /2)C i = ECE 663 Notice Boundary Condition !!

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Local Potential vs Gate voltage V G = V fb + s + ( s t ox / ox ) √(2kTN A / 0 s )[ s + e s -2 B ) ] 1/2 Initially, all voltage drops across channel (blue curve). Above threshold, channel potential stays pinned to 2 B, varying only logarithmically, so that most of the gate voltage drops across the oxide (red curve). ox ss

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Look at Effective charge width Initially, a fast increasing channel potential drops across increasing depletion width Eventually, a constant potential drops across a decreasing inversion layer width, so field keeps increasing and thus matches increasing field in oxide ~W dm /2 ~t inv

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Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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Charge vs Local Potential Q s ≈ √(2 0 s kTN A )[ s + e s -2 B ) ] 1/2 Beyond threshold, all charge goes to inversion layer

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How do we get the curvatures? EXACT Add other terms and keep Leading term NEW

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Inversion Charge vs Gate voltage Q ~ e s -2 B), s - 2 B ~ log(V G -V T ) Exponent of a logarithm gives a linear variation of Q inv with V G Q inv = -C ox (V G -V T ) Why C ox ?

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Questions What is the MOS capacitance? Q S ( S ) What are the local conditions during inversion? S,cr How does the potential vary with position? (x) How much inversion charge is generated at the surface? Q inv (x, S ) Add in the oxide: how does the voltage divide? S (V G ), ox (V G ) How much gate voltage do you need to invert the channel? V TH How much inversion charge is generated by the gate? Q inv (V G ) What’s the overall C-V of the MOSFET? Q S (V G )

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ECE 663 Capacitance For s =0 (Flat Band): Expand exponentials…..

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ECE 663 Capacitance of whole structure Two capacitors in series: C i - insulator C D - Depletion OR

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ECE 663 Capacitance vs Voltage

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ECE 663 Flat Band Capacitance Negative voltage = accumulation – C~C i Zero voltage – Flat Band

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ECE 663 CV As voltage is increased, C goes through minimum (weak inversion) where d /dQ is fairly flat C will increase with onset of strong inversion Capacitance is an AC measurement Only increases when AC period long wrt minority carrier lifetime At “high” frequency, carriers can’t keep up – don’t see increased capacitance with voltage For Si MOS, “high” frequency = Hz

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ECE 663 CV Curves – Ideal MOS Capacitor

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ECE 663 But how can we operate gate at today’s clock frequency (~ 2 GHz!) if we can’t generate minority carriers fast enough (> 100 Hz) ?

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ECE 663 MOScap vs MOSFET

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ECE 663 Substrate Drain Insulator Gate SourceChannel Substrate Insulator Gate Channel Minority carriers generated by RG, over minority carrier lifetime ~ 100 s So C inv can be << C ox if fast gate switching (~ GHz) Majority carriers pulled in from contacts (fast !!) C inv = C ox MOScap vs MOSFET

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ECE 663 Example Metal-SiO 2 -Si N A = /cm 3 At room temp kT/q = 0.026V n i = 9.65x10 9 /cm 3 s = 11.9x1.85x F/cm

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ECE 663 Example Metal-SiO 2 -Si d=50 nm thick oxide=10 -5 cm i =3.9x8.85x F/cm

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ECE 663 Real MIS Diode: Metal(poly)-Si-SiO 2 MOS Work functions of gate and semiconductor are NOT the same Oxides are not perfect –Trapped, interface, mobile charges –Tunneling All of these will effect the CV characteristic and threshold voltage

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ECE 663 Band bending due to work function difference

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ECE 663 Work Function Difference q s =semiconductor work function = difference between vacuum and Fermi level q m =metal work function q ms =(q m - q s ) For Al, q m =4.1 eV n + polysilicon q s =4.05 eV p + polysilicon q s =5.05 eV q ms varies over a wide range depending on doping

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ECE 663

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SiO 2 -Si Interface Charges

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ECE 663 Standard nomenclature for Oxide charges: Q M =Mobile charges (Na+/K+) – can cause unstable threshold shifts – cleanliness has eliminated this issue Q OT =Oxide trapped charge – Can be anywhere in the oxide layer. Caused by broken Si-O bonds – caused by radiation damage e.g. alpha particles, plasma processes, hot carriers, EPROM

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ECE 663 Q F = Fixed oxide charge – positive charge layer near (~2mm) Caused by incomplete oxidation of Si atoms(dangling bonds) Does not change with applied voltage Q IT =Interface trapped charge. Similar in origin to Q F but at interface. Can be pos, neg, or neutral. Traps e - and h during device operation. Density of Q IT and Q F usually correlated-similar mechanisms. Cure is H anneal at the end of the process. Oxide charges measured with C-V methods

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ECE 663 Effect of Fixed Oxide Charges

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ECE 663

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Surface Recombination Lattice periodicity broken at surface/interface – mid-gap E levels Carriers generated-recombined per unit area

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ECE 663 Interface Trapped Charge - Q IT Surface states – R-G centers caused by disruption of lattice periodicity at surface Trap levels distributed in band gap, with Fermi-type distributed: Ionization and polarity will depend on applied voltage (above or below Fermi level Frequency dependent capacitance due to surface recombination lifetime compared with measurement frequency Effect is to distort CV curve depending on frequency Can be passivated w/H anneal – /cm 2 in Si/SiO 2 system

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ECE 663 Effect of Interface trapped charge on C-V curve

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ECE 663 a – ideal b – lateral shift – Q oxide, ms c – distorted by Q IT

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ECE 663 Non-Ideal MOS capacitor C-V curves Work function difference and oxide charges shift CV curve in voltage from ideal case CV shift changes threshold voltage Mobile ionic charges can change threshold voltage as a function of time – reliability problems Interface Trapped Charge distorts CV curve – frequency dependent capacitance Interface state density can be reduced by H annealing in Si-Si0 2 Other gate insulator materials tend to have much higher interface state densities

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ECE 663 All of the above…. For the three types of oxide charges the CV curve is shifted by the voltage on the capacitor Q/C When work function differences and oxide charges are present, the flat band voltage shift is:

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Some important equations in the inversion regime (Depth direction) V T = ms + 2 B + ox W dm = [2 S (2 B )/qN A ] Q inv = C ox (V G - V T ) ox = Q s /C ox Q s = qN A W dm V T = ms + 2 B + ( [4 S B qN A ] - Q f + Q m + Q ot )/C ox Substrate Channel Drain Insulator Gate Source x

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