Download presentation

1
MOSFETs MOSFETs ECE 663

2
A little bit of history.. MOSFETs ECE 663

3
**Operation of a transistor**

VSG > 0 n type operation VSD VSG Gate Insulator More electrons Source Drain Channel Substrate Positive gate bias attracts electrons into channel Channel now becomes more conductive

4
**Operation of a transistor**

VSD VSG Gate Insulator Source Drain Channel Substrate Transistor turns on at high gate voltage Transistor current saturates at high drain bias

5
**Start with a MOS capacitor**

Substrate Channel Drain Insulator Gate Source VSD VSG

6
**MIS Diode (MOS capacitor) – Ideal**

MOSFETs MIS Diode (MOS capacitor) – Ideal ECE 663

7
**Questions What is the MOS capacitance? QS(yS) W**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) W

8
**Ideal MIS Diode n-type, Vappl=0**

MOSFETs EC EF EV Ei Assume Flat-band at equilibrium qfS ECE 663

9
**Ideal MIS Diode n-type, Vappl=0**

MOSFETs ECE 663

10
**Ideal MIS Diode p-type, Vappl=0**

MOSFETs ECE 663

11
**Ideal MIS Diode p-type, Vappl=0**

MOSFETs ECE 663

12
MOSFETs Accumulation Pulling in majority carriers at surface ECE 663

13
**But this increases the barrier for current flow !!**

MOSFETs But this increases the barrier for current flow !! n p n+ ECE 663

14
MOSFETs Depletion ECE 663

15
**Inversion yB Need CB to dip below EF.**

MOSFETs Inversion yB Need CB to dip below EF. Once below by yB, minority carrier density trumps the intrinsic density. Once below by 2yB, it trumps the major carrier density (doping) ! ECE 663

16
**Sometimes maths can help…**

MOSFETs Sometimes maths can help… ECE 663

17
**P-type semiconductor Vappl0**

MOSFETs P-type semiconductor Vappl0 Convention for p-type: y positive if bands bend down ECE 663

18
**Ideal MIS diode – p-type**

MOSFETs Ideal MIS diode – p-type CB moves towards EF if y > 0 n increases VB moves away from EF if y > 0 p decreases ECE 663

19
**Ideal MIS diode – p-type**

MOSFETs Ideal MIS diode – p-type At the semiconductor surface, = s ECE 663

20
**Surface carrier concentration**

MOSFETs Surface carrier concentration EC s < 0 - accumulation of holes s =0 - flat band B> s >0 – depletion of holes s =B - intrinsic concentration ns=ps=ni s > B – Inversion (more electrons than holes) EF ECE 663

21
**Want to find , E-field, Capacitance**

MOSFETs Want to find , E-field, Capacitance Solve Poisson’s equation to get E field, potential based on charge density distribution(one dimension) E E E ECE 663

22
**Away from the surface, = 0**

MOSFETs Away from the surface, = 0 and ECE 663

23
**Solve Poisson’s equation:**

MOSFETs Solve Poisson’s equation: E = -dy/dx d2y/dx2 = -dE/dx = (dE/dy).(-dy/dx) = EdE/dy EdE/dy ECE 663

24
**Solve Poisson’s equation:**

MOSFETs Solve Poisson’s equation: Do the integral: LHS: RHS: Get expression for E field (d/dx): ECE 663

25
**y > 0 y < 0 Define: Debye Length Then: E > 0 E < 0**

MOSFETs Define: Debye Length Then: E > 0 y > 0 y < 0 E < 0 + for > 0 and – for < 0 ECE 663

26
**Use Gauss’ Law to find surface charge per unit area**

MOSFETs Use Gauss’ Law to find surface charge per unit area ECE 663

27
**Accumulation to depletion to strong Inversion**

MOSFETs Accumulation to depletion to strong Inversion For negative , first term in F dominates – exponential For small positive , second term in F dominates - As gets larger, second exponential gets big yB = (kT/q)ln(NA/ni) = (1/b)ln(pp0/√pp0np0) (np0/pp0) = e-2byB yS > 2yB ECE 663

28
**Questions What is the MOS capacitance? QS(yS)**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG)

29
**Charges, fields, and potentials**

MOSFETs Charges, fields, and potentials Charge on metal = induced surface charge in semiconductor No charge/current in insulator (ideal) metal insul semiconductor depletion inversion ECE 663

30
**Charges, fields, and potentials**

MOSFETs Charges, fields, and potentials Electric Field Electrostatic Potential ECE 663

31
**Depletion Region Electric Field Electrostatic Potential ECE 663**

MOSFETs Depletion Region Electric Field Electrostatic Potential ECE 663

32
**y = ys(1-x/W)2 yB = (kT/q)ln(NA/ni) Depletion Region**

MOSFETs Depletion Region Electric Field Electrostatic Potential y = ys(1-x/W)2 Wmax = 2es(2yB)/qNA yB = (kT/q)ln(NA/ni) ECE 663

33
**Questions What is the MOS capacitance? QS(yS)**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG)

34
**Couldn’t we just solve this exactly?**

35
**Exact Solution F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2 U = by US = byS**

MOSFETs U = by US = byS UB = byB dy/dx = -(2kT/qLD)F(yB,np0/pp0) dU/F(U) = x/LD U US F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2

36
**Exact Solution r = qni[eUB(e-U-1) – e-UB(eU-1)]**

MOSFETs r = qni[eUB(e-U-1) – e-UB(eU-1)] dU’/F(U’,UB) = x/LD U US F(U,UB) = [eUB(e-U-1+U) + e-UB (eU-1-U)]1/2

37
**Exact Solution Qinv ~ 1/(x+x0)a x0 ~ LD . factor NA = 1.67 x 1015**

MOSFETs NA = 1.67 x 1015 Qinv ~ 1/(x+x0)a x0 ~ LD . factor

38
**Questions What is the MOS capacitance? QS(yS)**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG)

39
**Threshold Voltage for Strong Inversion**

MOSFETs Threshold Voltage for Strong Inversion Total voltage across MOS structure= voltage across dielectric plus s ECE 663

40
**Notice Boundary Condition !!**

MOSFETs Notice Boundary Condition !! eoxVi/tox = esys/(W/2) Before Inversion After inversion there is a discontinuity in D due to surface Qinv Vox (at threshold) = es(2yB)/(Wmax/2)Ci = ECE 663

41
**Local Potential vs Gate voltage**

VG = Vfb + ys + (kstox/kox) √(2kTNA/e0ks)[bys + eb(ys-2yB)]1/2 yox ys Initially, all voltage drops across channel (blue curve). Above threshold, channel potential stays pinned to 2yB, varying only logarithmically, so that most of the gate voltage drops across the oxide (red curve).

42
**Look at Effective charge width**

~Wdm/2 ~tinv Initially, a fast increasing channel potential drops across increasing depletion width Eventually, a constant potential drops across a decreasing inversion layer width, so field keeps increasing and thus matches increasing field in oxide

43
**Questions What is the MOS capacitance? QS(yS)**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG)

44
**Charge vs Local Potential**

Qs ≈ √(2e0kskTNA)[bys + eb(ys-2yB)]1/2 Beyond threshold, all charge goes to inversion layer

45
**How do we get the curvatures?**

NEW How do we get the curvatures? Add other terms and keep Leading term EXACT

46
**Inversion Charge vs Gate voltage**

Q ~ eb(ys-2yB), ys- 2yB ~ log(VG-VT) Exponent of a logarithm gives a linear variation of Qinv with VG Qinv = -Cox(VG-VT) Why Cox?

47
**Questions What is the MOS capacitance? QS(yS)**

What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG)

48
**Capacitance For s=0 (Flat Band): Expand exponentials….. ECE 663**

MOSFETs Capacitance For s=0 (Flat Band): Expand exponentials….. ECE 663

49
**Capacitance of whole structure**

MOSFETs Capacitance of whole structure Two capacitors in series: Ci - insulator CD - Depletion OR ECE 663

50
**Capacitance vs Voltage**

MOSFETs Capacitance vs Voltage ECE 663

51
**Flat Band Capacitance Negative voltage = accumulation – C~Ci**

MOSFETs Flat Band Capacitance Negative voltage = accumulation – C~Ci Zero voltage – Flat Band ECE 663

52
MOSFETs CV As voltage is increased, C goes through minimum (weak inversion) where d/dQ is fairly flat C will increase with onset of strong inversion Capacitance is an AC measurement Only increases when AC period long wrt minority carrier lifetime At “high” frequency, carriers can’t keep up – don’t see increased capacitance with voltage For Si MOS, “high” frequency = Hz ECE 663

53
**CV Curves – Ideal MOS Capacitor**

MOSFETs CV Curves – Ideal MOS Capacitor ECE 663

54
**But how can we operate gate at today’s clock frequency (~ 2 GHz!) **

MOSFETs But how can we operate gate at today’s clock frequency (~ 2 GHz!) if we can’t generate minority carriers fast enough (> 100 Hz) ? ECE 663

55
MOSFETs MOScap vs MOSFET ECE 663

56
**MOScap vs MOSFET Minority carriers generated by**

MOSFETs MOScap vs MOSFET Substrate Insulator Gate Substrate Drain Insulator Gate Source Channel Channel Minority carriers generated by RG, over minority carrier lifetime ~ 100ms So Cinv can be << Cox if fast gate switching (~ GHz) Majority carriers pulled in from contacts (fast !!) Cinv = Cox ECE 663

57
**Example Metal-SiO2-Si NA = 1017/cm3 At room temp kT/q = 0.026V**

MOSFETs Example Metal-SiO2-Si NA = 1017/cm3 At room temp kT/q = 0.026V ni = 9.65x109/cm3 s = 11.9x1.85x10-14 F/cm ECE 663

58
**Example Metal-SiO2-Si d=50 nm thick oxide=10-5 cm**

MOSFETs Example Metal-SiO2-Si d=50 nm thick oxide=10-5 cm i=3.9x8.85x10-14 F/cm ECE 663

59
**Real MIS Diode: Metal(poly)-Si-SiO2 MOS**

MOSFETs Real MIS Diode: Metal(poly)-Si-SiO2 MOS Work functions of gate and semiconductor are NOT the same Oxides are not perfect Trapped, interface, mobile charges Tunneling All of these will effect the CV characteristic and threshold voltage ECE 663

60
**Band bending due to work function difference**

MOSFETs Band bending due to work function difference ECE 663

61
**Work Function Difference**

MOSFETs Work Function Difference qs=semiconductor work function = difference between vacuum and Fermi level qm=metal work function qms=(qm- qs) For Al, qm=4.1 eV n+ polysilicon qs=4.05 eV p+ polysilicon qs=5.05 eV qms varies over a wide range depending on doping ECE 663

62
MOSFETs ECE 663

63
**SiO2-Si Interface Charges**

MOSFETs SiO2-Si Interface Charges ECE 663

64
**Standard nomenclature for Oxide charges: **

MOSFETs Standard nomenclature for Oxide charges: QM=Mobile charges (Na+/K+) – can cause unstable threshold shifts – cleanliness has eliminated this issue QOT=Oxide trapped charge – Can be anywhere in the oxide layer. Caused by broken Si-O bonds – caused by radiation damage e.g. alpha particles, plasma processes, hot carriers, EPROM ECE 663

65
**QF= Fixed oxide charge – positive charge layer **

MOSFETs QF= Fixed oxide charge – positive charge layer near (~2mm) Caused by incomplete oxidation of Si atoms(dangling bonds) Does not change with applied voltage QIT=Interface trapped charge. Similar in origin to QF but at interface. Can be pos, neg, or neutral. Traps e- and h during device operation. Density of QIT and QF usually correlated-similar mechanisms. Cure is H anneal at the end of the process. Oxide charges measured with C-V methods ECE 663

66
**Effect of Fixed Oxide Charges**

MOSFETs Effect of Fixed Oxide Charges ECE 663

67
MOSFETs ECE 663

68
**Surface Recombination**

MOSFETs Surface Recombination Lattice periodicity broken at surface/interface – mid-gap E levels Carriers generated-recombined per unit area ECE 663

69
**Interface Trapped Charge - QIT**

MOSFETs Interface Trapped Charge - QIT Surface states – R-G centers caused by disruption of lattice periodicity at surface Trap levels distributed in band gap, with Fermi-type distributed: Ionization and polarity will depend on applied voltage (above or below Fermi level Frequency dependent capacitance due to surface recombination lifetime compared with measurement frequency Effect is to distort CV curve depending on frequency Can be passivated w/H anneal – 1010/cm2 in Si/SiO2 system ECE 663

70
**Effect of Interface trapped charge on C-V curve**

MOSFETs Effect of Interface trapped charge on C-V curve ECE 663

71
**b – lateral shift – Q oxide, ms c – distorted by QIT**

MOSFETs a – ideal b – lateral shift – Q oxide, ms c – distorted by QIT ECE 663

72
**Non-Ideal MOS capacitor C-V curves**

MOSFETs Non-Ideal MOS capacitor C-V curves Work function difference and oxide charges shift CV curve in voltage from ideal case CV shift changes threshold voltage Mobile ionic charges can change threshold voltage as a function of time – reliability problems Interface Trapped Charge distorts CV curve – frequency dependent capacitance Interface state density can be reduced by H annealing in Si-Si02 Other gate insulator materials tend to have much higher interface state densities ECE 663

73
MOSFETs All of the above…. For the three types of oxide charges the CV curve is shifted by the voltage on the capacitor Q/C When work function differences and oxide charges are present, the flat band voltage shift is: ECE 663

74
**Some important equations in the inversion regime (Depth direction)**

Substrate Channel Drain Insulator Gate Source VT = fms + 2yB + yox x yox = Qs/Cox Qs = qNAWdm Wdm = [2eS(2yB)/qNA] VT = fms + 2yB + ([4eSyBqNA] - Qf + Qm + Qot)/Cox Qinv = Cox(VG - VT)

Similar presentations

OK

Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment – Poly-Si gate depletion effect Reading: Pierret 18.2-18.3; Hu.

Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment – Poly-Si gate depletion effect Reading: Pierret 18.2-18.3; Hu.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on work and energy class 11 Run ppt on raspberry pi Games we play ppt on tv Ppt on network layer in computer networks Ppt on fire extinguisher types for electronics Ppt on social impact of information technology Ppt on means of transport for class 2 Ppt on production management Ppt on ict in teaching Ppt on gender in hindi