Presentation on theme: "Week #2 Slides. Agenda Recap 15 Years of Evolution to Virtex Four generations of Spartan Project discussion Questions."— Presentation transcript:
Week #2 Slides
Agenda Recap 15 Years of Evolution to Virtex Four generations of Spartan Project discussion Questions
XC2000 Family – The Original
First Configuration Logic Block
First IO Cell Note: having All user pins be I/O was a big DEAL!!!
XC3000 Family CLB Second Generation
XC3000 Fabric Array Little black dots Are PIPs
XC3000 IO Cell
XC4000 CLB Third Generation
XC4000 IO Cell Note
VIRTEX The Fourth Generation NOTE: VIRTEX Equated with Having hard Fixed blocks Embedded in The fabric
… which brings us to Spartan 3 (uh, we did skip a bunch of stuff, but the progression for our needs works out...)
Spartan 3 Xilinx and the industry track silicon technology – micron – 1 micron – 0.8 to 0.35 micron – 0.25 micron, micron – Spartan 3 & Virtex 90 nm – Virtex nm – Spartan 45 nm – Virtex 40 nm – Etc.
Spartan Philosophy Offer a more cost effective solution for higher volume markets Need to reduce costs to do that – Trim features – Reduce test cost – Sacrifice speed over die size – Cheaper packages – Etc. Spartan is the overall result
Spartan 3 Family Chart
Spartan 3 IO Cell Note
Heterogeneous Logic Cells
Stuff in Black & Grey Common to SliceL & sliceM Blue stuff in SliceM only
Some Block RAM Detail
Digital Clock Managers
Clock nets Do heavy lifting Different nets In each family FYI
Adjust the mix: Spartan 3E
Reduce the Banks: more IO pins available
Spartan 3E IO Cell Note
Adjustable Input Delay
Adjust the mix: Spartan 3A
Stack the Flash: Spartan 3AN A Single Chip Solution
Internal SPI Flash
Add a block: Spartan 3A DSP
Spartan 3A DSP Architecture
DSP48 with a Pre-Adder
Projects Depend On your knowledge Your skill level Your confidence Your interest Uh...I don’t know any of the above points about you! Only YOU know where you are at on this continuum My goal is to get you to where you can design on Xilinx FPGAs, which has a LOT to do with the S/W!
Some Ideas Interfaces – MIX & MATCH things Buses and memories Peripherals & memories Buses & peripherals Processors & the above Systems – Build single function items – Combine two or more items – Invent something new
Ahh, the Good Old Days... Basic idea: Create useful, correct standard functions then... HOOK ‘EM UP!
My All Time Favorite Part
Ahh, the Good NEW Days!
Graphic stolen from Doug Smith’s Book cover...I’m looking for the CD that was optional
Stolen From Smith Like Old TTL Manual
Uh, also stolen from Smith... NOTE!!!!
Modern Way to Design... Follow the LIGHT!!
Possible Projects The Light bulb area has design templates for both VHDL and Verilog I’d like to expand the documentation on them along the lines of the TTL Catalog, and Doug Smith’s book. Need volunteers to take say 10 of the templates, instantiate into a design, capture the schematic (automatic) and simulate to verify the operation
Possible Project Continued The Deliverable would be a WORD file organized to have: – Template code – Graphic – Simulation I can make these available to the rest of the class and to future classes
Another Idea The Digilent NEXYS2 board is supported by VHDL solutions, which are available. Most of them are 1-2 sheets of code. I’d like to get them in Verilog, with simulations and compiled onto Xilinx Spartan 3 parts. Take a look at the “pmod” code chunks
One more thing to remember Your project should you obtain your goal for this class – May be to log some credit to a credential – May be to learn something about FPGAs – May be to design something you always wanted an excuse to design – I won’t know what that is... – It’s up to you