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Reachability analysis A reachability analysis shows the product space of the two processes and the signal queues of their input ports. Say we have an SDL system. The diagrams on the following slides show the interface between a pair of processes A and B in the system.

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The SDL Block containing two processes

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Two communicating SDL Processes

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To perform the reachability analysis, the first step is to transform the process graph into transition charts. In a transition chart, each input is prefixed with a “?” and each output by a “!”. Each transition consists of either an input or an output. Reachability analysis (How to do a State Space exploration)

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The Transition chart for the SDL Processes

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Assuming that there is a maximum queue size of 1, this is the global graph for the transition charts. State space exploration

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State Space exploration graph

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Possible errors Unspecified receptions –An unspecified reception occurs when a state in the global behavior is scheduled to receive a message that it does not know how to handle Queue overflow –This occurs when there is an attempt to put a signal in a queue that is already full

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Possible errors(continued) Deadlocks –deadlocks can also occur when 2 or more processes are unable to proceed because they wait endlessly for signals from each other. Livelocks –livelocks occur when processes send signals endlessly without making any progress.

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Deriving role behaviours Now the global behaviour graph grows very rapidly. For large systems, we need to simplify the job. One method is deriving role behaviours.

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Deriving role behaviours Steps to follow: –Mark the transitions that involve signals to and from the environment with the special symbol. These transitions are called invisible transitions. –Find the set of nodes reachable from a given node by following one or more -transitions (called -ambiguities) and group them together. –We have a reduced transition chart. Then, proceed as usual.

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The Modified Transition chart with -transitions

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(without the -transitions)

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The new State-Space exploration graph

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Tau tool We can explore the state space by using the validator in Telelogic Tau tool. When a random walk is done, the tool will randomly select a branch and move down the graph until it reaches an unspecified reception,a deadlock or the end of the graph (maximum depth specified). It then selects randomly another branch. The following is the output given when the random walk was done on the egg timer system.

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Click here to Start the Bit-State or Random Walk state space exploration or to go step by step through the specification use the navigator

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A bit-state can also be done. The bit-state will attempt to find all the possible outcomes from the top node. From these, it will repeat the same operation and go through their possible outcomes. The following is the output of the bit-state search in the validator.

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