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The BTeV Level 1 Muon Trigger Update Michael J. Haney 27 January 2001 www.hep.uiuc.edu/engin/btev/reports/27jan01.ppt (and.pdf)

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Presentation on theme: "The BTeV Level 1 Muon Trigger Update Michael J. Haney 27 January 2001 www.hep.uiuc.edu/engin/btev/reports/27jan01.ppt (and.pdf)"— Presentation transcript:

1 The BTeV Level 1 Muon Trigger Update Michael J. Haney 27 January (and.pdf)

2 Algorithm compress adjacent tube hits and AND/OR (selectable) RR views working radially inward, form valid RR 2 -U 2 pairs (fixed table size => outer bias) look-up V 2 ‘s from RRU 2 ‘s; form RRUV 2 ’s –and RRV 2 ’s and UV 2 ’s, etc. as space/time permits R U V

3 Algorithm (continued) window-search RR 3 ’s based on RRUV 2 ’s look-up U 3 ’s and V 3 ’s from RRUV 2 RR 3 ’s look-up RR 1 ’s, U 1 ’s, V 1 ’s from RRUV 2 RRUV 3 ’s declare RRUV 1 RRUV 2 RRUV 3 ’s (and various lessers) as “tracks” calculate  2 ’s (?)

4 Algorithm Notes radially-inward processing –biased in favor of higher P T –implications on front end readout (order) fixed table sizes –accommodates “wall of fire” near beam pipe octant-arm specific –16-fold symmetry in hardware –no inter-octant communications

5 Algorithm Notes (continued) combinatoric explosion - suppressed –RRU 2 ’s require O(N 2 ) –“look-up” steps require O(M) –window search? O(M) to O(M 2 ) could be fully implemented in the Pixel Trigger DSP Farm –but compression/table-building may be done in (Pixel Trigger?) FPGAs

6 Status Fortran code to analyze efficiency –work-in-progress DSP code implementation –next FPGA implementation (table building) –next


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